Dear Community,I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction.
a) I cannot clearly understand the meaning of Burst size signals - ARSIZE and AWSIZE.When there are Bust length signals -AWLEN, ARLEN, which specifies the number of data transactions, whey we need another signal for burst size? Isn't the bust length info enough to specify how many transaction we need master to do?
b) Burst Address
Can someone please explain how AXI decides the next address of transaction in Bust mode? In the spec there is some equation, but I cannot clearly understand it.
Please see below the simulation waveform, I want to understand the Burst behavioral here:
Here the awaddr is always 0, but burst type is 1 which means we are dealing with increment burst.
The behavioral of awlen, awsize signals are not clear for me. Also awcache signal is not clear
Can someone please explain
1) How many data will be written
2) In which addresses
3) What is awcache value showing?