C164- DPPx: how to find data in Memory window???

Hi Stefan,
I'm sorry, but there is something wrong in your calculations: Hannes said

Does DPP2:0x220A means ( 3 <<14) | 0x220A ?
Result would be 0xE20A ??

and

Where content of DPP2 is 3

This is correct, address is 0xE20A.
In fact the correct formula would be
((DPP2 & 0x03FF) << 14) | (0x220A & 0x3FFF)
you will obtain 0x30220A only if you set DDP2 to 0x00C0.
Ciao
Bruno

Hi Stefan,
I'm sorry, but there is something wrong in your calculations: Hannes said

Does DPP2:0x220A means ( 3 <<14) | 0x220A ?
Result would be 0xE20A ??

and

Where content of DPP2 is 3

This is correct, address is 0xE20A.
In fact the correct formula would be
((DPP2 & 0x03FF) << 14) | (0x220A & 0x3FFF)
you will obtain 0x30220A only if you set DDP2 to 0x00C0.
Ciao
Bruno

Bruno,

you are absolut right.
If I said 10 bit value, I did the wrong shifting.
Hannes,
Sorry for confusion, that was my mistake.

PageOffset(14bit).....xx10 0010 0000 1010
DPP2 = 10b.............1010 0010 0000 1010
(10bit)
DPP2value=3h =>.....xxxx xx00 0000 0011

Address:
00 0000 0011 xx xxxx xxxx xxxx
xx .xxxx xx10 10 0010 0000 1010
-------------------------------
00 0000 0011 10 0010 0000 1010
= 00'E20Ah

Stefan

Hi Bruno,
that's me again. Now I am confused.

Assuming the DPP2 value is 5=101b.
PageOffset from Hannes is 0x220Ah.
For DPP2= 10b

I got with my calculating:

00 0000 0101 00 0000 0000 0000
00 0000 0010 10 0010 0000 1010
---------------------------------------
00 0000 0111 10 0010 0000 1010 = 01'E20Ah

00 0000 0101 00 0000 0000 0000
00 0000 0000 10 0010 0000 1010 because mask
---------------------------------------
00 0000 0101 10 0010 0000 1010 = 01'620Ah

Hello Stefan,
the C167 hardware compose the 24 bit address using the formula I gave you, but this does not mean that it really makes the shift and mask operations written into the formula; operations are just done into a dedicated part of the C167 hardware.
Bits 14 and 15 of the PageOffset just select the DPPx register to be used to compose the full 24 bit address.
Imagine the C167 hardware that composes the 24 bit address: it should be very similar to this schematic diagram

                4 to 1 Multiplexer
                    +-------+
            DPP0 --->       |
                    |       |
            DPP1 --->  \    |
                    |   o-- >----+
            DPP2 --->       |    |
                    |       |    |
            DPP3 --->       |    |
                    +---^---+    |
                        |        |
                        |        |
      2 bit selector    |        +--> Address bits 14..24
      Bits 14 and 15 >--+        +--> Address bits 0.13
     from PageOffset             |
                                 |
                                 |
    Bits 0..13 from PageOffset >-+

<--DPPx----> <---PageOffset-->
00 0000 0101 00 0000 0000 0000
00 0000 0000 10 0010 0000 1010
---------------------------------------
00 0000 0101 10 0010 0000 1010 = 01'620Ah

Hi Bruno, hi Hannes,

I am shamed, but enlighted.
Bruno, no doubt anymore. It is all correct.
I read with your explanation the users manual very carefully again.
(I misinterpreted the fig.4-14 in the
systems users manual XC167CI V1.1 2002
page 4-34 ..... page 4-36,
where bits 14 and 15 are shown separated)

Correct formula by Bruno is

((DPP2 & 0x03FF) << 14) | (0x220A & 0x3FFF)

Hello Mr. Coppi!
... it's nice to know You are there watching the 'S.O.S' messages.

Please could You explain how the compiler translates?: I looked at this line of code:

000002F4 F2F50AA2 MOV R5,DPP2:0x220A

and wondered why the address is 0xE20A, I expected 0xA20A, -the difference is one page 0x4000, I think. But how does the C164 know that? How is the right DPPreg (DPP2) used (because everywhere a DPP is used, a 'F' is written at the place where the registers are addressed: F2F50AA2).



...I don't know if i asked You times ago, but i am confused everytime i use the PWM (CapCom6): the CC6x register seems to be a shadow register because the duty cycle only changes after setting STE12. All the Manuals say it's not. Also Errata sheets tells nothing other. Do You know something? (I used B and C steps).

Best Regards hannes

Ciao Hannes,

... it's nice to know You are there watching the 'S.O.S' messages.

I ALWAYS read the forum (at night), even if I answer questions very seldom.

How is the right DPPreg (DPP2) used (because everywhere a DPP is used, a 'F' is written at the place where the registers are addressed: F2F50AA2).

Well, I'm not sure I understand your question; you want to know WHERE is the binary field that selects the DPPx into that opcode? It is in bits 14 and 15 of the address:
F2F5 is the opcode itself
A20A is the address
A20A = 10.10 0010 0000 1010
the leftmost 2 bits (10.) are the DPP selection bitfield (in this case 10. = 2, so DPP2 is selected), the remaining 14 bits (.10 0010 0000 1010) are the address within a 16K page.

Please could You explain how the compiler translates?

I can only guess: during the code generation, the compiler 'knows' how DPP registers are used and keeps track of their content.
So, when it generates a memory access instruction, first of all it looks at the DPP registers and composes the instruction using the correct bitfield to address the required DPP.
Anyway, things can be different for each memory model and I'm not the compiler writer, this is only an hypothesis and it's better you ask Reinhard Keil directly to have further informations about compiler technology.

About CC6x registers: they have shadow latches.

C164 User's Manual V3.1, 2002-02, page 17-22

Shadow Latches for Synchronous Update

The timer period, offset, and compare values are written to shadow latches rather than
to the actual registers. Also the initial value bits CCxI/COUTxI in register CC6MCON are
equipped with shadow latches. Thus the values for a new output signal can be
programmed without disturbing the currently generated signal(s). The transfer from the
latches to the registers is enabled by setting the respective shadow latch transfer enable
bit STEx in register CTCON.
If the transfer is enabled the shadow latches are copied to the respective registers the
next time the associated timer reaches the value zero (either being cleared in edge
aligned mode or counting down from 1 in center aligned mode).
When timer T12 is operating in center aligned mode it will also copy the latches (if
enabled) if it reaches the currently programmed period value (counting up).
After the transfer the respective bit STEx is automatically cleared.
Note: While T12/T13 is running, the shadow latch transfer is controlled by bit STE12/13.
While T12/T13 is stopped, the shadow latch transfer is done automatically if bit
CTRES12/13 is set; otherwise those latch values are not transferred.
Note: If a new compare value is written to the shadow latches while T12 is counting up,
the new value must be smaller than the current period value. Otherwise no more
matches will be detected and the output signals will no longer change.
If a compare value is written, while T12 is counting down, any value may be used.