Dear Sirs! I would like to observe data in Memory window. For example this line of code was build from the compiler: 000002F4 F2F50AA2 MOV R5,DPP2:0x220A Where content of DPP2 is '3'. Does DPP2:0x220A means ( 3 <<14) | 0x220A ? Result would be 0xE20A ?? F2F50AA2 says to me the Address 0xA20A will be read...(0x220A - 0x8000 = 0xA20A???) in the memory window of the Debugger the contents of these addresses are just 0x00!? How can I take a look at the right addresses? Please write an answer to my Question! hannes
Ciao Hannes, ... it's nice to know You are there watching the 'S.O.S' messages. I ALWAYS read the forum (at night), even if I answer questions very seldom. How is the right DPPreg (DPP2) used (because everywhere a DPP is used, a 'F' is written at the place where the registers are addressed: F2F50AA2). Well, I'm not sure I understand your question; you want to know WHERE is the binary field that selects the DPPx into that opcode? It is in bits 14 and 15 of the address: F2F5 is the opcode itself A20A is the address A20A = 10.10 0010 0000 1010 the leftmost 2 bits (10.) are the DPP selection bitfield (in this case 10. = 2, so DPP2 is selected), the remaining 14 bits (.10 0010 0000 1010) are the address within a 16K page. Please could You explain how the compiler translates? I can only guess: during the code generation, the compiler 'knows' how DPP registers are used and keeps track of their content. So, when it generates a memory access instruction, first of all it looks at the DPP registers and composes the instruction using the correct bitfield to address the required DPP. Anyway, things can be different for each memory model and I'm not the compiler writer, this is only an hypothesis and it's better you ask Reinhard Keil directly to have further informations about compiler technology. About CC6x registers: they have shadow latches.
C164 User's Manual V3.1, 2002-02, page 17-22 Shadow Latches for Synchronous Update The timer period, offset, and compare values are written to shadow latches rather than to the actual registers. Also the initial value bits CCxI/COUTxI in register CC6MCON are equipped with shadow latches. Thus the values for a new output signal can be programmed without disturbing the currently generated signal(s). The transfer from the latches to the registers is enabled by setting the respective shadow latch transfer enable bit STEx in register CTCON. If the transfer is enabled the shadow latches are copied to the respective registers the next time the associated timer reaches the value zero (either being cleared in edge aligned mode or counting down from 1 in center aligned mode). When timer T12 is operating in center aligned mode it will also copy the latches (if enabled) if it reaches the currently programmed period value (counting up). After the transfer the respective bit STEx is automatically cleared. Note: While T12/T13 is running, the shadow latch transfer is controlled by bit STE12/13. While T12/T13 is stopped, the shadow latch transfer is done automatically if bit CTRES12/13 is set; otherwise those latch values are not transferred. Note: If a new compare value is written to the shadow latches while T12 is counting up, the new value must be smaller than the current period value. Otherwise no more matches will be detected and the output signals will no longer change. If a compare value is written, while T12 is counting down, any value may be used.