Hi
i'm working with SAM3 microcontroller with 12MHz external crystal and set the multiplier and divider to have 64MHz for Master Clock then i see mistake when code is running
it's necessary noted that boundary condition for SAM3S is 64MHz for master clock does it have relation to this parameter and should this condition satisfy at all cost
Ok, can you present the code you have, and the frequency you are actually observing. When posting code, please read/review the instructions for doing so.
The math and settings required can't be unduly complicated.
The limits would tend to be one of maximal pll/vco speeds, and flash wait states
Hi pier and thanks for your reply, I should first apologize for not answering. I was very busy and I thought my problem was resolved I did not even check the forum for reply. But lately I understood that the problem is still there.
As for the code, here is the system_sam3s.c file which contains the most of configuration relating to the system frequency. Is it sufficient or you need to check on other files as well?
As for PLL and wait states I double checked the data sheet and I believe I am meeting the requirements correctly. you may check in the presented code as well. But I can not understand what you meant by VCO. may you explain what is VCO?
I cant post the code completely because of the length limit so I split it in 2 parts.
/* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ /*--------------------- Embedded Flash Controllers Configuration ------------- // // <e0> Embedded Flash Controller (EEFC) // <o1.8..11> FWS: Flash Wait State <1-16><#-1> // <o1.24> FAM: Flash Access Mode // <0=> 128-bit in read mode (enhance speed) // <1=> 64-bit in read mode (enhance power consumption) // </e0> */ #define EEFC_SETUP 1 // Reset values: #define EEFC_FMR_Val 0x00000200 // 0x00000000 /*--------------------- Power Management Controller Configuration ------------ // // <e> Power Management Controller (PMC) // <h> System Clock Enable Register (PMC_SCER) // <o1.7> UDP: USB Device Port Clock Enable // <o1.8> PCK0: Programmable Clock 0 Output Enable // <o1.9> PCK1: Programmable Clock 1 Output Enable // <o1.10> PCK2: Programmable Clock 2 Output Enable // </h> // // <h> Peripheral Clock Enable Register 0 (PMC_PCER0) // <o2.2> PID2: Real Time Clock Clock Enable // <o2.3> PID3: Real Time Timer Clock Enable // <o2.4> PID4: Watchdog Timer Clock Enable // <o2.5> PID5: Power Management Controller Clock Enable // <o2.6> PID6: Enhanced Embedded Flash Controller Clock Enable // <o2.8> PID8: UART 0 Clock Enable // <o2.9> PID9: UART 1 Clock Enable Clock Enable // <o2.10> PID10: Static Memory Controller Clock Enable // <o2.11> PID11: Parallel I/O Controller A Clock Enable // <o2.12> PID12: Parallel I/O Controller B Clock Enable // <o2.13> PID13: Parallel I/O Controller C Clock Enable // <o2.14> PID14: USART 0 Clock Enable // <o2.15> PID15: USART 1 Clock Enable // <o2.16> PID16: USART 2 Clock Enable // <o2.18> PID18: Multimedia Card Interface Clock Enable // <o2.19> PID19: Two-wire Interface 0 Clock Enable // <o2.20> PID20: Two-wire Interface 1 Clock Enable // <o2.21> PID21: Serial Peripheral Interface Clock Enable // <o2.22> PID22: Synchronous Serial Controller Clock Enable // <o2.23> PID23: Timer Counter 0 Clock Enable // <o2.24> PID24: Timer Counter 1 Clock Enable // <o2.25> PID25: Timer Counter 2 Clock Enable // <o2.26> PID26: Timer Counter 3 Clock Enable // <o2.27> PID27: Timer Counter 4 Clock Enable // <o2.28> PID28: Timer Counter 5 Clock Enable // <o2.29> PID29: Analog-to-Digital Converter Clock Enable // <o2.30> PID30: Digital-to-Analog Converter Clock Enable // <o2.31> PID31: Pulse Width Modulation Clock Enable // </h> // // <h> Peripheral Clock Enable Register 1 (PMC_PCER1) // <o3.0> PID32: CRC Calculation Unit Clock Enable // <o3.1> PID33: Analog Comparator Clock Enable // <o3.2> PID34: USB Device Port Clock Enable // </h> // // <h> Main Oscillator Register (CKGR_MOR) // <o4.0> MOSCXTEN: Main Crystal Oscillator Enable // <o4.1> MOSCXTBY: Main Crystal Oscillator Bypass // <o4.2> WAITMODE: Wait Mode Command // <o4.3> MOSCRCEN: Main On-chip RC Oscillator Enable // <o4.4..6> MOSCRCF: Main On-chip RC Oscillator Frequency Selection // <0=> 4MHz <1=> 8 MHz <2=> 12 MHz <3=> Reserved // <o4.8..15> MOSCXTST: Main Crystal Oscillator Startup Time <0-255> // <o4.24> MOSCSEL: Main Oscillator Selection // <0=> Main On-chip RC Oscillator <1=> Main Crystal Oscillator // <o4.25> CFDEN: Clock Failure Detector Enable // </h> // // <h> Clock Generator Phase Locked Loop A Register (CKGR_PLLAR) // PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1) // Example: XTAL = 12 MHz, DIVA = 1, MULA = 14 => PLLA = 168 MHz // <o5.0..7> DIVA: PLL Divider A <0-255> // 0 - Divider output is 0 // 1 - Divider is bypassed // 2 .. 255 - Divider output is the Main Clock divided by DIVA // <o5.8..13> PLLACOUNT: PLL A Counter <0-63> // Number of Slow Clocks before the LOCKA bit is set in // PMC_SR after CKGR_PLLAR is written // <o5.16..26> MULA: PLL A Multiplier <0-2047> // 0 - The PLL A is deactivated // 1 .. 2047 - The PLL A Clock frequency is the PLLA input // frequency multiplied by MULA + 1 // </h> //
please concat the 2 parts and use keil configuration wizard to check it.
// <h> Clock Generator Phase Locked Loop B Register (CKGR_PLLBR) // PLL B Freq = (Main CLOCK Freq / DIVB) * (MULB + 1) // Example: XTAL = 12 MHz, DIVB = 1, MULB = 14 => PLLB = 168 MHz // <o6.0..7> DIVB: PLL Divider B <0-255> // 0 - Divider output is 0 // 1 - Divider is bypassed // 2 .. 255 - Divider output is the Main Clock divided by DIVB // <o6.8..13> PLLBCOUNT: PLL B Counter <0-63> // Number of Slow Clocks before the LOCKB bit is set in // PMC_SR after CKGR_PLLBR is written // <o6.16..26> MULB: PLL B Multiplier <0-2047> // 0 - The PLL B is deactivated // 1 .. 2047 - The PLL B Clock frequency is the PLLB input // frequency multiplied by MULB + 1 // </h> // // <h> Master Clock Register (PMC_MCKR) // <o7.0..1> CSS: Master Clock Selection // <0=> Slow Clock // <1=> Main Clock // <2=> PLL A Clock // <3=> PLL B Clock // <o7.4..6> PRES: Master Clock Prescaler // <0=> Clock <1=> Clock / 2 // <2=> Clock / 4 <3=> Clock / 8 // <4=> Clock / 16 <5=> Clock / 32 // <6=> Clock / 64 <7=> Clock / 3 // <o7.12> PLLADIV2: PLLA Divisor by 2 // <o7.13> PLLBDIV2: PLLB Divisor by 2 // </h> // // <h> USB Clock Register (PMC_USB) // <o8.0> USBS: USB Input Clock Selection // <0=> PLLA Clock // <1=> PLLB Clock // <o8.8..11> USBDIV: USB Input Clock Devider <0-15> // USB Clock is Input clock divided by USBDIV+1 // </h> // // <h> Programmable Clock Register 0 (PMC_PCK0) // <o9.0..2> CSS: Master Clock Selection // <0=> Slow Clock // <1=> Main Clock // <2=> PLLA Clock // <3=> PLLB Clock // <4=> Master Clock // <5=> Master Clock // <6=> Master Clock // <7=> Master Clock // <o9.4..6> PRES: Programmable Clock Prescaler // <0=> Clock <1=> Clock / 2 // <2=> Clock / 4 <3=> Clock / 8 // <4=> Clock / 16 <5=> Clock / 32 // <6=> Clock / 64 <7=> Reserved // </h> // // <h> Programmable Clock Register 1 (PMC_PCK1) // <o10.0..2> CSS: Master Clock Selection // <0=> Slow Clock // <1=> Main Clock // <2=> PLLA Clock // <3=> PLLB Clock // <4=> Master Clock // <5=> Master Clock // <6=> Master Clock // <7=> Master Clock // <o10.4..6> PRES: Programmable Clock Prescaler // <0=> None <1=> Clock / 2 // <2=> Clock / 4 <3=> Clock / 8 // <4=> Clock / 16 <5=> Clock / 32 // <6=> Clock / 64 <7=> Reserved // </h> // // <h> Programmable Clock Register 2 (PMC_PCK2) // <o11.0..2> CSS: Master Clock Selection // <0=> Slow Clock // <1=> Main Clock // <2=> PLLA Clock // <3=> PLLB Clock // <4=> Master Clock // <5=> Master Clock // <6=> Master Clock // <7=> Master Clock // <o11.4..6> PRES: Programmable Clock Prescaler // <0=> None <1=> Clock / 2 // <2=> Clock / 4 <3=> Clock / 8 // <4=> Clock / 16 <5=> Clock / 32 // <6=> Clock / 64 <7=> Reserved // </h> // </e> */ #define PMC_SETUP 1 // Reset values: #define PMC_SCER_Val 0x00000000 // WO register (0x00000001) #define PMC_PCER0_Val 0x00A08000 // WO register (0x00000000) #define PMC_PCER1_Val 0x00001C04 // WO register (0x00000000) #define CKGR_MOR_Val 0x01370F01 // 0x00000001 #define CKGR_PLLAR_Val 0x201F0603 // 0x00003F00 #define CKGR_PLLBR_Val 0x20070601 // 0x00003F00 #define PMC_MCKR_Val 0x00000012 // 0x00000001 #define PMC_USB_Val 0x00000101 // 0x00000000 #define PMC_PCK0_Val 0x00000000 // 0x00000000 #define PMC_PCK1_Val 0x00000000 // 0x00000000 #define PMC_PCK2_Val 0x00000000 // 0x00000000 /*--------------------- Watchdog Configuration ------------------------------- // // <e> Watchdog Disable // </e> */ #define WDT_SETUP 1 // Reset values: /* //-------- <<< end of configuration section >>> ------------------------------ */
For summarizing the configuration: Let me explain the configuration in case you don't want to check the code thoroughly.
Flash wait state : 3 Flash Access Mode : 128 bit
PLLA: devider : 3 counter : 6 multiplier : 31
PLLB: devider : 1 counter : 6 multiplier : 7
MCK source : PLLA MCK prescaler : clock/2
USB clock source : PLLB USBDIV : 1
Really doesn't appear to be any code there and the math clearly won't get you too 64 MHz
>> i see mistake when code is running Ok, so WHAT SPEED do you see?
PLLA: divider : 2 counter : 6 multiplier : 31 PLLB: divider : 1 counter : 6 multiplier : 7 MCK source : PLLA MCK prescaler : clock/2 USB clock source : PLLB USBDIV : 1
12 MHz / (2 + 1) * (31 + 1) / 2
12 / 3 * 32 / 2
4 * 32 / 2
128 / 2
64 MHz
VCO - Voltage Controlled Oscillator, silicon base rapid pulse generator, with a tuning/control voltage changing the frequency.
The PLL doesn't have a "multiplier" it runs a VCO at a high frequency, tuning it, and dividing it down to a common comparison frequency, in this case 4 MHz
Thanks for the reply, sorry I've made a mistake in my post and wrote the wrong configured value for PLLA divider. the configured value is not 2 it is configured to be 3 and multiplier is 31 as the datasheet indicates the PLL output clock will be: ((MUL+1)* PLL input) / DIV no +1 for DIV so my PLL output is : ((31+1) * 12) / 3 32*4 = 128
and as for master clock source is PLLA & prescaler is clock/2 so my master clock is 128/2 = 64 MHz
and as for VCO, I think you are referring to the internal oscillator. Am I right? If this is the case then I think it must be irrelevant to my problem because I am using the external oscillator as PLLA source.
As I said the MCK frequency seems to be configured correctly. so if you agree please read the rest of the description.
The problem is not the speed or frequency I see. I did not even think of measuring the MCK. The problem I encounter is here: I have a simple cryptographic algorithm (namely DES) being executed in my main loop (this is a test program that shows the board error).
In case you are not familiar with cryptography, let me explain that the algorithm transforms a plain input message to a ciphered message using an encryption key. if the key and the message are the same then the same encrypted result should be output each time you execute the algorithm.
in my main loop, I repeatedly compute the DES output for a specific key and input. At first the results do match but as time passes the result mismatches, causing my main loop to break and turning on an LED as failure indicator. My analysis to this point has given the below observations: 1.Some micro-controllers fail but some do not fail this test. 2.MCK frequency is a sensitive parameter in this test. micro-controllers that fail with MCK = 64 will not fail with lower frequency like 55 MHz. 3.If i heat up the hardware board using a hot air blower the micro controller fails sooner (the temperature was measured during heating up and it was in the operational temperature range, <85 degrees of centigrade). and if I lower the board temperature artificially the failure will not occur.
I know I posted too much information. I wait for you to read this then I will give more information as you want.
>>and as for VCO, I think you are referring to the internal oscillator. Am I right?
No, I'm talking about a VCO, not an RC oscillator, how do you think PLL's works, magically pulling a higher frequency out of the air? How does a frequency "multiplier" work?
Perhaps you should be discussing the failure of the ATMEL part, with ATMEL? This isn't a Keil issue, go find an FAE.
I'd verify the frequency, and check on any external PLL filter circuits, supplies, and bulk capacitance.
I use an external crystal oscillator with 12 MHZ output. This is the source of my PLL. Ok. I will check the PLL related issues as you said.
But the failure is discussed with Atmel. they've done all sorts of 'I don't exactly understand' tests and answered the parts and our hardware boards were ok and passed all the tests.
So I think the problem should reside in configuration. The problem is really complicated. So I will be glad if you can answer one basic question.
Is configuring a micro-controller at max frequency for master clock wrong? is it discouraged? Or the maximum stated frequency is safe to use at any condition? (considering wait states and other limitations)
Unless there is an errata, then the frequency should be supported for the full temperature range and all other conditions.
The basic exception is that a processor might support a rather wide voltage span. And then there might be multiple maximum frequencies specified in the datasheet depending on which voltage range it is operating in.
But the operating frequency, number of rewrites of the flash memory is basically worst-case guarantees where the devices are expected to have enough safety margins.
Thanks for your help Per