Hi
i'm working with SAM3 microcontroller with 12MHz external crystal and set the multiplier and divider to have 64MHz for Master Clock then i see mistake when code is running
it's necessary noted that boundary condition for SAM3S is 64MHz for master clock does it have relation to this parameter and should this condition satisfy at all cost
please concat the 2 parts and use keil configuration wizard to check it.
// <h> Clock Generator Phase Locked Loop B Register (CKGR_PLLBR) // PLL B Freq = (Main CLOCK Freq / DIVB) * (MULB + 1) // Example: XTAL = 12 MHz, DIVB = 1, MULB = 14 => PLLB = 168 MHz // <o6.0..7> DIVB: PLL Divider B <0-255> // 0 - Divider output is 0 // 1 - Divider is bypassed // 2 .. 255 - Divider output is the Main Clock divided by DIVB // <o6.8..13> PLLBCOUNT: PLL B Counter <0-63> // Number of Slow Clocks before the LOCKB bit is set in // PMC_SR after CKGR_PLLBR is written // <o6.16..26> MULB: PLL B Multiplier <0-2047> // 0 - The PLL B is deactivated // 1 .. 2047 - The PLL B Clock frequency is the PLLB input // frequency multiplied by MULB + 1 // </h> // // <h> Master Clock Register (PMC_MCKR) // <o7.0..1> CSS: Master Clock Selection // <0=> Slow Clock // <1=> Main Clock // <2=> PLL A Clock // <3=> PLL B Clock // <o7.4..6> PRES: Master Clock Prescaler // <0=> Clock <1=> Clock / 2 // <2=> Clock / 4 <3=> Clock / 8 // <4=> Clock / 16 <5=> Clock / 32 // <6=> Clock / 64 <7=> Clock / 3 // <o7.12> PLLADIV2: PLLA Divisor by 2 // <o7.13> PLLBDIV2: PLLB Divisor by 2 // </h> // // <h> USB Clock Register (PMC_USB) // <o8.0> USBS: USB Input Clock Selection // <0=> PLLA Clock // <1=> PLLB Clock // <o8.8..11> USBDIV: USB Input Clock Devider <0-15> // USB Clock is Input clock divided by USBDIV+1 // </h> // // <h> Programmable Clock Register 0 (PMC_PCK0) // <o9.0..2> CSS: Master Clock Selection // <0=> Slow Clock // <1=> Main Clock // <2=> PLLA Clock // <3=> PLLB Clock // <4=> Master Clock // <5=> Master Clock // <6=> Master Clock // <7=> Master Clock // <o9.4..6> PRES: Programmable Clock Prescaler // <0=> Clock <1=> Clock / 2 // <2=> Clock / 4 <3=> Clock / 8 // <4=> Clock / 16 <5=> Clock / 32 // <6=> Clock / 64 <7=> Reserved // </h> // // <h> Programmable Clock Register 1 (PMC_PCK1) // <o10.0..2> CSS: Master Clock Selection // <0=> Slow Clock // <1=> Main Clock // <2=> PLLA Clock // <3=> PLLB Clock // <4=> Master Clock // <5=> Master Clock // <6=> Master Clock // <7=> Master Clock // <o10.4..6> PRES: Programmable Clock Prescaler // <0=> None <1=> Clock / 2 // <2=> Clock / 4 <3=> Clock / 8 // <4=> Clock / 16 <5=> Clock / 32 // <6=> Clock / 64 <7=> Reserved // </h> // // <h> Programmable Clock Register 2 (PMC_PCK2) // <o11.0..2> CSS: Master Clock Selection // <0=> Slow Clock // <1=> Main Clock // <2=> PLLA Clock // <3=> PLLB Clock // <4=> Master Clock // <5=> Master Clock // <6=> Master Clock // <7=> Master Clock // <o11.4..6> PRES: Programmable Clock Prescaler // <0=> None <1=> Clock / 2 // <2=> Clock / 4 <3=> Clock / 8 // <4=> Clock / 16 <5=> Clock / 32 // <6=> Clock / 64 <7=> Reserved // </h> // </e> */ #define PMC_SETUP 1 // Reset values: #define PMC_SCER_Val 0x00000000 // WO register (0x00000001) #define PMC_PCER0_Val 0x00A08000 // WO register (0x00000000) #define PMC_PCER1_Val 0x00001C04 // WO register (0x00000000) #define CKGR_MOR_Val 0x01370F01 // 0x00000001 #define CKGR_PLLAR_Val 0x201F0603 // 0x00003F00 #define CKGR_PLLBR_Val 0x20070601 // 0x00003F00 #define PMC_MCKR_Val 0x00000012 // 0x00000001 #define PMC_USB_Val 0x00000101 // 0x00000000 #define PMC_PCK0_Val 0x00000000 // 0x00000000 #define PMC_PCK1_Val 0x00000000 // 0x00000000 #define PMC_PCK2_Val 0x00000000 // 0x00000000 /*--------------------- Watchdog Configuration ------------------------------- // // <e> Watchdog Disable // </e> */ #define WDT_SETUP 1 // Reset values: /* //-------- <<< end of configuration section >>> ------------------------------ */