Hi
i'm working with SAM3 microcontroller with 12MHz external crystal and set the multiplier and divider to have 64MHz for Master Clock then i see mistake when code is running
it's necessary noted that boundary condition for SAM3S is 64MHz for master clock does it have relation to this parameter and should this condition satisfy at all cost
Hi pier and thanks for your reply, I should first apologize for not answering. I was very busy and I thought my problem was resolved I did not even check the forum for reply. But lately I understood that the problem is still there.
As for the code, here is the system_sam3s.c file which contains the most of configuration relating to the system frequency. Is it sufficient or you need to check on other files as well?
As for PLL and wait states I double checked the data sheet and I believe I am meeting the requirements correctly. you may check in the presented code as well. But I can not understand what you meant by VCO. may you explain what is VCO?
I cant post the code completely because of the length limit so I split it in 2 parts.
/* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ /*--------------------- Embedded Flash Controllers Configuration ------------- // // <e0> Embedded Flash Controller (EEFC) // <o1.8..11> FWS: Flash Wait State <1-16><#-1> // <o1.24> FAM: Flash Access Mode // <0=> 128-bit in read mode (enhance speed) // <1=> 64-bit in read mode (enhance power consumption) // </e0> */ #define EEFC_SETUP 1 // Reset values: #define EEFC_FMR_Val 0x00000200 // 0x00000000 /*--------------------- Power Management Controller Configuration ------------ // // <e> Power Management Controller (PMC) // <h> System Clock Enable Register (PMC_SCER) // <o1.7> UDP: USB Device Port Clock Enable // <o1.8> PCK0: Programmable Clock 0 Output Enable // <o1.9> PCK1: Programmable Clock 1 Output Enable // <o1.10> PCK2: Programmable Clock 2 Output Enable // </h> // // <h> Peripheral Clock Enable Register 0 (PMC_PCER0) // <o2.2> PID2: Real Time Clock Clock Enable // <o2.3> PID3: Real Time Timer Clock Enable // <o2.4> PID4: Watchdog Timer Clock Enable // <o2.5> PID5: Power Management Controller Clock Enable // <o2.6> PID6: Enhanced Embedded Flash Controller Clock Enable // <o2.8> PID8: UART 0 Clock Enable // <o2.9> PID9: UART 1 Clock Enable Clock Enable // <o2.10> PID10: Static Memory Controller Clock Enable // <o2.11> PID11: Parallel I/O Controller A Clock Enable // <o2.12> PID12: Parallel I/O Controller B Clock Enable // <o2.13> PID13: Parallel I/O Controller C Clock Enable // <o2.14> PID14: USART 0 Clock Enable // <o2.15> PID15: USART 1 Clock Enable // <o2.16> PID16: USART 2 Clock Enable // <o2.18> PID18: Multimedia Card Interface Clock Enable // <o2.19> PID19: Two-wire Interface 0 Clock Enable // <o2.20> PID20: Two-wire Interface 1 Clock Enable // <o2.21> PID21: Serial Peripheral Interface Clock Enable // <o2.22> PID22: Synchronous Serial Controller Clock Enable // <o2.23> PID23: Timer Counter 0 Clock Enable // <o2.24> PID24: Timer Counter 1 Clock Enable // <o2.25> PID25: Timer Counter 2 Clock Enable // <o2.26> PID26: Timer Counter 3 Clock Enable // <o2.27> PID27: Timer Counter 4 Clock Enable // <o2.28> PID28: Timer Counter 5 Clock Enable // <o2.29> PID29: Analog-to-Digital Converter Clock Enable // <o2.30> PID30: Digital-to-Analog Converter Clock Enable // <o2.31> PID31: Pulse Width Modulation Clock Enable // </h> // // <h> Peripheral Clock Enable Register 1 (PMC_PCER1) // <o3.0> PID32: CRC Calculation Unit Clock Enable // <o3.1> PID33: Analog Comparator Clock Enable // <o3.2> PID34: USB Device Port Clock Enable // </h> // // <h> Main Oscillator Register (CKGR_MOR) // <o4.0> MOSCXTEN: Main Crystal Oscillator Enable // <o4.1> MOSCXTBY: Main Crystal Oscillator Bypass // <o4.2> WAITMODE: Wait Mode Command // <o4.3> MOSCRCEN: Main On-chip RC Oscillator Enable // <o4.4..6> MOSCRCF: Main On-chip RC Oscillator Frequency Selection // <0=> 4MHz <1=> 8 MHz <2=> 12 MHz <3=> Reserved // <o4.8..15> MOSCXTST: Main Crystal Oscillator Startup Time <0-255> // <o4.24> MOSCSEL: Main Oscillator Selection // <0=> Main On-chip RC Oscillator <1=> Main Crystal Oscillator // <o4.25> CFDEN: Clock Failure Detector Enable // </h> // // <h> Clock Generator Phase Locked Loop A Register (CKGR_PLLAR) // PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1) // Example: XTAL = 12 MHz, DIVA = 1, MULA = 14 => PLLA = 168 MHz // <o5.0..7> DIVA: PLL Divider A <0-255> // 0 - Divider output is 0 // 1 - Divider is bypassed // 2 .. 255 - Divider output is the Main Clock divided by DIVA // <o5.8..13> PLLACOUNT: PLL A Counter <0-63> // Number of Slow Clocks before the LOCKA bit is set in // PMC_SR after CKGR_PLLAR is written // <o5.16..26> MULA: PLL A Multiplier <0-2047> // 0 - The PLL A is deactivated // 1 .. 2047 - The PLL A Clock frequency is the PLLA input // frequency multiplied by MULA + 1 // </h> //