Hi,
I'm using the STM32F103ZET6 uC on the MCBSTM32E board. Our company is developing a PCB with two of those uC on it communicating with each other through SPI. As the PCB is not developed yet I would like to test these inter-SPI communication by interconnection SPI1 and SPI2 on the MCBSTM32E board. I connected SPI1 to SPI2 one on one meaning with their SCK/NSS/MOSI/MISO signals. So for example SPI1.SCK is connected to SPI2.SCK, e.t.c.. I use swapping from GPIO to AFN (Alternate function) for controlling two on the fly changing configurations: 1: SPI1-master/SPI2-slave (with DMA) 2: SPI2-master/SPI1-slave (with DMA) From SPI1 to SPI2 it works fine. From SPI2 to SPI1 the receiving SPI1 only generates SPI1-RXNE (rx buffer not empty) interrupts for the first 4 bytes and then simply does not occur anymore although receiving SCK and MOSI data is still active and DMA buffer size is set to 100. SPI2 generates SPI2-RXNE interrupts for all received (26) bytes.
I tried and studied lots of hours but could not find the cause. The Errata pdf mentions some issues with SPI's but not this kind.
Anybody any idea?
Thanks
Henk
So for example SPI1.SCK is connected to SPI2.SCK, e.t.c.. SCK1 to SCK2 (assuming _of the same controller_)!!! REALLY?
What makes my head spin is, which clock is driving which spi?
So for example SPI1.SCK is connected to SPI2.SCK, e.t.c.. MOSI to MOSI and MISO to MISO ... makes my head spin is it correct way?
Yes - the two clocks should be connected to each other. What would be strange with that? The slave needs to see the same bit clock that the master is using. Just that the master might support a larger range of baudrates than the device - it depends a bit of implementation details in the specific chip.
And MOSI on one interface (Master Out Slave In) should be connected to MISO (Master In Slave Out) of the other interface. Setting one interface as master and one as slave, will decide which side will drive the MISO pin
When A is master MOSI => MOSI MISO <= MISO
When B is master MOSI <= MOSI MISO => MISO
Note that SPI is a bus design, where there can be more than two devices on the bus that may transmit. That means that the interconnects must be straight.
Then depending on design, you might connect slave-select to slave-select and configure the pin as GPIO for the master and as slave-select for the slave. Or configre it as slave-select for both devices, while configuring the SPI master to actively control the slave-select line.
"which clock is driving which spi"
Easy.
The side that is configured as master will emit a clock. The side that is configured as slave will listen to the clock.
This is all standard SPI. That is why it is so simple to have multiple masters on the same SPI bus. You just implement some way to hand over which device that will be master and take control of the clock signal, the MOSI signal and drive one or more slave-select signals. All other devices has to be slaves, so listening on MOSI and slave-select and (potentially) sending on MISO. A SPI slave can normally decide if it will send on MISO or not - this feature is needed to allow multiple slaves to listen to MISO without fighting over the MISO signal.
another strange effect...
Setting the RXNE interrupt generates an interrupt each time the receive buffer is not empty. The reference manual states: Clearing of the RXNE bit is performed by reading the SPI_DR register.
Well does it?... the bit also gets cleared if NOT reading the DR register. My SPI2_IRQHandler just counts entries and toggles an I/O-pin and I see it toggle 26 times for receiving 26 bytes. Even if I choose a very low transmission speed 26 edges are generated... This means that at least for SPI2 the RXNE means 'Byte received' in stead of 'Rx Buffer Not Empty'. In latter case I would expect only one interrupt call when not reading the DR data register.
Oops (Sorry). Ya, realized it that it can be done.
Not another strange effect...
I did not realize that the SPI is controlled by DMA(!) so the DMA takes care of reading received data from de SPI-DR register which reading action then automatically clears the RXNE bit.
sorry...
But the first mentioned problem concerning the SPI1 receive interrupt generating only 4 interrupt calls still exists.
SCK1 to SCK2 (assuming _of the same controller_)!!! REALLY?
I do not know if you got that this is an absolute no-no
it seems you are trying to make a "dual master SPI" NOT possible (without some fancy en/disable circuitry)
The only SPI device that is allowed to clock is the Master!
MOSI to MOSI and MISO to MISO ... makes my head spin if you spell it out, the spinning stops
MasterOutSlaveIn and MasterInSlaveOut
Erik
If the SPI is set to slave mode then all 4 signals are set to tri-state/high-impedance by the slave.
MOSI to MOSI and MISO to MISO is adapted from the SPI part example in the datasheet of the microcontroller.
Quote: "The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first)."
Also data can get out of the MOSI or MISO pin depending on the internal configuration.
It works fine from SPI1 to SPI2 but not vice versa although ALL data of 10 Bytes IS received by SPI1's DMA rx-channel buffer but the SPI's RXNE interrupt stops being called after having received the first 4 of 10 bytes. I suspect the DMA rx-channel is somehow not correctly connected to SPI1.
do you set the master to read before you set it to write?
do not know your code but, write before read could lead to occasionally missed interrupts.
But the master will both read and write so should happen at same time - so same initialization.
But the slave needs to be fully initialized before the master starts the transfer.
"I do not know if you got that this is an absolute no-no
it seems you are trying to make a "dual master SPI" NOT possible (without some fancy en/disable circuitry)"
No. He is testing code that is intended to run on two different processors, by using his single processor to talk with his self. So test both SPI1 master, SPI2 slave. And SPI1 slave, SPI2 master. So SCK1 connected to SCK2 is a requirement for this. For one test, SCK1 is output and SCK2 is input. For next test they reverse direction.
So no dual-master involved.