Hi,
I'm using the STM32F103ZET6 uC on the MCBSTM32E board. Our company is developing a PCB with two of those uC on it communicating with each other through SPI. As the PCB is not developed yet I would like to test these inter-SPI communication by interconnection SPI1 and SPI2 on the MCBSTM32E board. I connected SPI1 to SPI2 one on one meaning with their SCK/NSS/MOSI/MISO signals. So for example SPI1.SCK is connected to SPI2.SCK, e.t.c.. I use swapping from GPIO to AFN (Alternate function) for controlling two on the fly changing configurations: 1: SPI1-master/SPI2-slave (with DMA) 2: SPI2-master/SPI1-slave (with DMA) From SPI1 to SPI2 it works fine. From SPI2 to SPI1 the receiving SPI1 only generates SPI1-RXNE (rx buffer not empty) interrupts for the first 4 bytes and then simply does not occur anymore although receiving SCK and MOSI data is still active and DMA buffer size is set to 100. SPI2 generates SPI2-RXNE interrupts for all received (26) bytes.
I tried and studied lots of hours but could not find the cause. The Errata pdf mentions some issues with SPI's but not this kind.
Anybody any idea?
Thanks
Henk
"I do not know if you got that this is an absolute no-no
it seems you are trying to make a "dual master SPI" NOT possible (without some fancy en/disable circuitry)"
No. He is testing code that is intended to run on two different processors, by using his single processor to talk with his self. So test both SPI1 master, SPI2 slave. And SPI1 slave, SPI2 master. So SCK1 connected to SCK2 is a requirement for this. For one test, SCK1 is output and SCK2 is input. For next test they reverse direction.
So no dual-master involved.