Hi all!
I bought Segger J-Link JTAG and I wanted to make a try with Logic Analyzer. I have unlocked debug state of my STM32F107 as described in Keil Help, made a simple while loop with incrementation like shown below: lh4.ggpht.com/.../trace1.jpg
and after I have run my program for several seconds, stopped it and I found I didnt record any result. I start and stop for several times, and that are the only positions Logic Analyzer recorded: lh4.ggpht.com/.../trace2.jpg
As you can see my trace have NOT been overflowed, and my debug settings looks like this: lh4.ggpht.com/.../trace3.jpg
even if I set more trace ports it is always the same :(
Hi,
Trace on SWO should work fine.
Trace on SWO is not a full Trace, you must choose a high divider for PC Sampling (1024 x ...) and enable PC sampling.
When you single Step in ASM (disassembly window) you may choose the lowest one, then you'll get nearly every instruction.
Trace with JTrace works fine.
. BR, /th.
I use the evaluation version. I get my var data in the watch tab, but no trace data of the same var in the logic analyzer? If i write somesthin to the ITM Cell, printf via ITM Stimulus Port, then i receive the data without problems. Do you use the JLink or the JTrace? Could there be a difference?
best regards,
Holger
I use JLINK and it is not working in my opinion with Logic Analyzer. It is sad because in Keil manual it is written it will work :(
Hi there,
meanwhile i have a full licence and checked again the Logic Analyzer.
I can say, YES it works, BUT the values are only updated if i enable the "Periodic Window Update". And the really poor behavior is, the values in the Logic Analyzer are only the sampled values of the "Periodic Window Update". So in the end the resolution depends on the sample time of the "Periodic Window Update". This is not acceptable in a real time application.
I know, that the SWO Trace is no full trace, but ITM Macros (printf) works fine and is sufficient, but why is that not possible with the Logic Analyzer?
If someone will change a ULink2 Adapter to my JLink, he can mail me. After some mails to segger with no response, i don't believe that there will be a solution in the next time... really sad..
Best regards
I have full license and Segger J-Link, but I wasnt able to make it work. Iv got globally declared volatile variable, trace turned on, uC clocked configured (in Trace option), turned on Periodic Sample, and so on just like on the pictures: img835.imageshack.us/.../72373182.gif img842.imageshack.us/.../42631512.gif
My code is:
volatile unsigned char logic=0; main() { while(1) { logic++; if( logic == 255 ) logic = 0; } }
All i get is constant random value (each time I restart the program it hangs on diffrent value) img692.imageshack.us/.../69582651.gif and it doesnt change. I know that variable will change rapidly, because of while(1), but even then there should be jitter value in logic analyzer, not constant value.
@Holger Fürstenberger Can You compare and tell me what Im doing wrong? What type of J-Link you have? Mine is V8 (non-trace).
Best regards, Maciej Andrzejewski.
Unrelated question but why the manual reset to zero of the variable? Being an unsigned 8-bit variable, it will turn around anyway on next increment.