Hi all!
I bought Segger J-Link JTAG and I wanted to make a try with Logic Analyzer. I have unlocked debug state of my STM32F107 as described in Keil Help, made a simple while loop with incrementation like shown below: lh4.ggpht.com/.../trace1.jpg
and after I have run my program for several seconds, stopped it and I found I didnt record any result. I start and stop for several times, and that are the only positions Logic Analyzer recorded: lh4.ggpht.com/.../trace2.jpg
As you can see my trace have NOT been overflowed, and my debug settings looks like this: lh4.ggpht.com/.../trace3.jpg
even if I set more trace ports it is always the same :(
I have full license and Segger J-Link, but I wasnt able to make it work. Iv got globally declared volatile variable, trace turned on, uC clocked configured (in Trace option), turned on Periodic Sample, and so on just like on the pictures: img835.imageshack.us/.../72373182.gif img842.imageshack.us/.../42631512.gif
My code is:
volatile unsigned char logic=0; main() { while(1) { logic++; if( logic == 255 ) logic = 0; } }
All i get is constant random value (each time I restart the program it hangs on diffrent value) img692.imageshack.us/.../69582651.gif and it doesnt change. I know that variable will change rapidly, because of while(1), but even then there should be jitter value in logic analyzer, not constant value.
@Holger Fürstenberger Can You compare and tell me what Im doing wrong? What type of J-Link you have? Mine is V8 (non-trace).
Best regards, Maciej Andrzejewski.
Unrelated question but why the manual reset to zero of the variable? Being an unsigned 8-bit variable, it will turn around anyway on next increment.