This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

SIMULATION

Hello, I have a problem simulating the ADuC7026's bau rate generation, I'd configured the UART to operate at 9600 bps, but when I debugged it says that generates 4800 bps...
What I'm Doing Wrong?

Thanks

JuanMa

  • "What I'm Doing Wrong?"

    You are not posting any source code, forcing readers to have to guess wildly.

  • I'm very sorry...
    As It doesn't work, I tough maybe it was a mistake of mine, so I've tried to compile the example of analog device, but it still saying that generate 4800 bps.

    /*********************************************************************
    
     Author        : ADI - Apps            www.analog.com/MicroConverter
    
     Date          : Sept. 2005
    
     File          : UART2.c
    
     Hardware      : Applicable to ADuC702x rev H or I silicon
                     Currently targetting ADuC7026.
    
     Description   : Read part of memory and output through UART (SPM0&1).
                                     The baudrate is calculated with the following formula:
    
                                            DL = HCLK
                                                    _______
                                                    Baudrate * 2 *16
    
                                     A 9600 8-N-1 Hyperterminal window is required to observe
                                     the results.
    
    *********************************************************************/
    #include <ADuC7026.h>
    
    
    void senddata(short);
    void delay(int);
    char hex2ascii(char);
    
    int main (void)  {
    
    static unsigned short SOMEDATA[1024];
    int i;
    
            GP0CON = 0x10000000;            // enable ECLK output on P0.5
    
            // configures GPIO to flash LED P4.2
            GP4DAT = 0x04000000;            // P4.2 configured as an output. LED is turned on
    
            // Setup tx & rx pins on SPM 0 and SPM 1
            GP1CON = 0x011;
    
         // Start setting up UART at 9600bps
            COMCON0 = 0x080;                        // Setting DLAB
            COMDIV0 = 0x088;                        // Setting DIV0 and DIV1 to DL calculated
            COMDIV1 = 0x000;
            COMCON0 = 0x007;                        // Clearing DLAB
    
            for (i=0; i <1024; i++)
            {
                    SOMEDATA[i]=i;
            }
    
            while(1)
            {
            for (i=0; i <1024; i++)
            {
                    senddata (SOMEDATA[i]);
            }
            GP4DAT ^= 0x00040000;           // Complement P4.2
            delay(2000);
            }
    }
    
    
    void delay (int length)
    {
            while (length >=0)
            length--;
    }
    
    void senddata(short to_send)
    {
            while(!(0x020==(COMSTA0 & 0x020))){}
                    COMTX = 0x0A;                                           // output LF
            while(!(0x020==(COMSTA0 & 0x020))){}
                    COMTX = 0x0D;                                           // output CR
            while(!(0x020==(COMSTA0 & 0x020))){}
                    COMTX = hex2ascii ((to_send >> 8) & 0x0F);
            while(!(0x020==(COMSTA0 & 0x020))){}
                    COMTX = hex2ascii ((to_send >> 4) & 0x0F);
            while(!(0x020==(COMSTA0 & 0x020))){}
                    COMTX = hex2ascii (to_send & 0x0F);
    }
    
    
    char hex2ascii(char toconv)
    {
            if (toconv<0x0A)
            {
                    toconv += 0x30;
            }
            else
            {
                    toconv += 0x37;
            }
    
            return (toconv);
    }
    
    

    And finally I can't understand why sends LF and CR.

    Thanks!

    JuanMa

  • The source code claims:
    DL = HCLK / (Baudrate * 2 *16)

    You initialize the baudrate divisor with 0x88.

    You haven't specified your HCLK, but is it close to:
    0x88 * 9600 * 2 * 16 = 41779200 Hz = 41.8MHz?

    What is trange with sending LF and CR? Where you thinking about the order of them? CR+LF is the expected order on a Windows system.

  • ahhh, I didn't know that about CR+LF. Yes it's 41,8Mhz, but I find the problem! It was PLL Setup, CD it was by default at 1, so cleared it.

    Thanks for your attention!!

    JuanMa