Hello, I have a problem simulating the ADuC7026's bau rate generation, I'd configured the UART to operate at 9600 bps, but when I debugged it says that generates 4800 bps... What I'm Doing Wrong?
Thanks
JuanMa
The source code claims: DL = HCLK / (Baudrate * 2 *16)
You initialize the baudrate divisor with 0x88.
You haven't specified your HCLK, but is it close to: 0x88 * 9600 * 2 * 16 = 41779200 Hz = 41.8MHz?
What is trange with sending LF and CR? Where you thinking about the order of them? CR+LF is the expected order on a Windows system.
ahhh, I didn't know that about CR+LF. Yes it's 41,8Mhz, but I find the problem! It was PLL Setup, CD it was by default at 1, so cleared it.
Thanks for your attention!!