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Hello,
We are working on 8051 project and the code size is large around 100 K with code banking. We are faceing some problem in our products, kindly give your valued suggestions.
We are using Keil PK51 Version 8.05 and Phillips 89c52X2BN micro controller.
1. How many functions can be nested in an Interrupt Service Routine(ISR) or what is the depth of functions called from ISR?
2. What could be the maximum code size of an Interrupt service Routine including its all sub-functions, if the interrupt occurs every 20 milliseconds?
3. If we are using Timer 0 interrupt and reloading the timer registers TL0 and TH0 at every ISR subroutine start, when should we set the timer run bit(TR0 = 1) _at start of ISR or at the end of ISR code(in order to generate an exact delay we wanted)?
4. What is the memory allocation pattern for xdata variables (used in our project) by Keil compiler or is there any basic allocation method followed by Keil compiler?
5. What are the disadvantages of using absolute memory accesses(using _at_ ) for xdata variables if I use 64K external RAM, and what is the burden on the 8051 core controller
6. What could be the maximum permissible code size of common area if I use code banking with 2 code banks? I dedicated 6150 bytes code for common area in my project. Is it justified?
7. I used optimization level 9 for my project compilation. What are the adverse effects on the 8051 core controller if I use this highest level? What are the advantages and disadvantages? With this level of optimization, my code size is 104Kbytes of total 128Kbytes.
8. Is there a maximum limit to the size of the memory allocated to a structure that is compiled by Keil? I am using structure variables which use 150 bytes of xdata space each. Can I use a single structure which uses this much memory space?
9. Datatype {long} is not being supported in my project. If I create a variable of type {long}, there are no errors in compilation. But, the system is not functioning / booting . Are there any limitations in using {long} type?
10. Will Keil compiler support Timer 2 interrupt usage, if I use Timer 2 interrupt in my project with 8052 processor?
11. What are the advantages and disadvantages for the 89C52X2 core controller if I use 6x clock speed of execution instead of default 12x speed
12. What could be the maximum code size of an individual function in a Keil-compiled project?
kindly advise.
That depends on your stack size.
The code size is not limited. The ISR could take up all available code space if necessary. The limiting factor would be the execution time of the ISR, which should of course be less than 20 ms, and much less than 20 ms if the processor is supposed to do anything else.
That depends on how precisely the execution time of the ISR is known. If the ISR has a fixed execution time, you may need to adjust the reload value, but the timer could be started at the end of the ISR. Of course, the easier way would be starting it at the beginning of the ISR.
The compiler does not allocate any memory in most cases. That is the job of the linker.
5. What are the disadvantages of using absolute memory accesses(using _at_ ) for xdata variables if I use 64K external RAM, and what is the burden on the 8051 core controller.
The MCU does not care who (compiler or linker) put a variable in a certain place. The burden is exactly the same. The disadvantages are that it's messy and that such variables cannot be initialized. It's usually better to leave this job to the linker.
That depends on your exact memory layout.
There aren't any adverse effects for MCU (why should there ? adverse effects would mean that the program is faulty). There may be adverse effects for the programmer, namely that highly optimized code is more difficult to debug. Also, bugs that were in the code before might have more noticable effects with high optimization settings.
The limit is only placed by the amount of available memory (there's no point of, for example, putting a 150 byte structure in idata space).
No, there are no limitiations (other than long arithmetics taking a long time on an 8 bit MCU, but that is not the fault of the compiler). If your system is not functioning, then the problem lies most, most likely in your code.
The compiler does not care about the hardware. Using the timer 2 interrupt is up to you.
The advantage is that the code runs twice as fast. The downside is that the code runs twice at fast, which may break timing loops, etc, that rely on a certain execution speed.
That depends on the ROM model used (small/compact/large, and not to be confused with the memory model) and the status of the compiler (full version or restricted/eval version). Other than that, one function may take up all available memory, there's no limit.
These questions all sound fairly theoretical and the answers are all readily available in the documentation. Are you sure this isn't homework ?
"1. How many functions can be nested in an Interrupt Service Routine(ISR) or what is the depth of functions called from ISR?"
The tools don't impose a limit.
However, it is generally a bad idea to call any functions at all from an ISR! The general principle is usually to keep ISRs as short and simple as possible - just doing the absolute minimum to handle the event and record any associated data. Any processing should be left to the main code.
"2. What could be the maximum code size of an Interrupt service Routine including its all sub-functions, if the interrupt occurs every 20 milliseconds?"
That will obviously depend upon your clock frequency - which I can't see in your post.
You can calculate this from the hardware interrupt latency, and the instruction execution times; eg, see: www.8052.com/.../read.phtml
"The downside is that the code runs twice at fast, which may break timing loops, etc, that rely on a certain execution speed."
If it runs faster, it will also consume more power..
"These questions all sound fairly theoretical and the answers are all readily available in the documentation."
It is a bit worrying that someone with a 100K project is still asking these questions...
1) As few as you can manage. An ISR should do _very_little_work_ so if you are worrying about nesting levels you are already doing too much.
2) Code size and runtime are not directly correlated. However, you should not perform any real work in the ISR, so the question shouldn't be important anyway.
3) Depends on which frequency to divide from.
4) I don't understand your question. It sounds more like a question to make for dyanmically allocated memory. The linker will place xdata variables directly after each other. The memory model will control what memory areas the Keil compiler should use - unless you specifically force the use of a memory region.
5) Let's reverse the question: What reason do you have for absolute positioning of your xdata variables?
6) Wouldn't 32k + 32k be a good partitioning? Or are you basically writing two separate applications, with the common are no more than basically a boot loader?
8) Depends on memory region. 150 byte xdata structs shouldn't be a problem.
9) Why isn't long supported? Have you read: http://www.keil.com/support/man/docs/c51/c51_ap_datastorage.htm I don't work with the C51, so someone will probably correct me now but: Have you checked if you need any 32-bit helper functions, and are they linked into the common code? 10) Why would the Keil compiler not support your processor? 11) Current consumption contra speed? 12) Have you written a too large function? In that case, I think it is in acute need of splitting.
We are using 11.0592 MHz Crystal. If we increase the crystal by 22.1184; what is the adverse effect other than modifying the timers etc.
As we are doing lot of memory mapped devices (IC's)
If you increase a 11.0592 MHz frequency by 22.1184 MHz, you will end up at 33.1776 MHz - is that what you really mean?
"what is the adverse effect"
Is your hardware properly designed for higher-frequency operation - particularly with respect to EMC?
"we are doing lot of memory mapped devices"
Changing the clock frequency will obviously affect the memory timings...
Increasing the clock speed sounds very much like a "band-aid" approach - ie, it just covers up the symptoms, without actually addressing the underlying cause(s)...
It sounds like you have a fundamentally under-powered hardware platform and/or fundamentally oversized and/or inefficient software
Remember, the 8051 is basically a simple architecture designed for no more than 64K of code...
1. How many functions can be nested in an Interrupt Service Routine(ISR) or what is the depth of functions called from ISR? in theory as many as you want, for good code NONE
2. What could be the maximum code size of an Interrupt service Routine including its all sub-functions, if the interrupt occurs every 20 milliseconds? in theory the number of instructions that you can exceute in 20ms, for good gode as few as possible
3. If we are using Timer 0 interrupt and reloading the timer registers TL0 and TH0 at every ISR subroutine start, when should we set the timer run bit(TR0 = 1) _at start of ISR or at the end of ISR code(in order to generate an exact delay we wanted)? you stop the timer at x and start it a y. The exact time is timer setting PLUS the instructions executed between x and y less what the timer reads a x.
4. What is the memory allocation pattern for xdata variables (used in our project) by Keil compiler or is there any basic allocation method followed by Keil compiler? do not understand the question
5. What are the disadvantages of using absolute memory accesses(using _at_ ) for xdata variables if I use 64K external RAM, and what is the burden on the 8051 core controller (dis)advantags: application dependent, burden: none
6. What could be the maximum permissible code size of common area if I use code banking with 2 code banks? I dedicated 6150 bytes code for common area in my project. Is it justified? Based on your questions, I believe you do not need code banking, just sensible code.
7. I used optimization level 9 for my project compilation. What are the adverse effects on the 8051 core controller if I use this highest level? What are the advantages and disadvantages? With this level of optimization, my code size is 104Kbytes of total 128Kbytes. the advantages of optimization is faster, smaller code, the disadvantage is you can not debug it.
8. Is there a maximum limit to the size of the memory allocated to a structure that is compiled by Keil? I am using structure variables which use 150 bytes of xdata space each. Can I use a single structure which uses this much memory space? I have had problems with structures that cross 64k. My experience with C51 is that as long as a structure is within one memory page it can be as large as you want.
9. Datatype {long} is not being supported in my project. If I create a variable of type {long}, there are no errors in compilation. But, the system is not functioning / booting . Are there any limitations in using {long} type? no project support any data type that is a job for the compiler
10. Will Keil compiler support Timer 2 interrupt usage, if I use Timer 2 interrupt in my project with 8052 processor? see answer to 6.
11. What are the advantages and disadvantages for the 89C52X2 core controller if I use 6x clock speed of execution instead of default 12x speed you run twice as fast DUH
12. What could be the maximum code size of an individual function in a Keil-compiled project? as long as you use code banking the size of the bank, when you get the code right 64k.
Erik