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Hello,
We are working on 8051 project and the code size is large around 100 K with code banking. We are faceing some problem in our products, kindly give your valued suggestions.
We are using Keil PK51 Version 8.05 and Phillips 89c52X2BN micro controller.
1. How many functions can be nested in an Interrupt Service Routine(ISR) or what is the depth of functions called from ISR?
2. What could be the maximum code size of an Interrupt service Routine including its all sub-functions, if the interrupt occurs every 20 milliseconds?
3. If we are using Timer 0 interrupt and reloading the timer registers TL0 and TH0 at every ISR subroutine start, when should we set the timer run bit(TR0 = 1) _at start of ISR or at the end of ISR code(in order to generate an exact delay we wanted)?
4. What is the memory allocation pattern for xdata variables (used in our project) by Keil compiler or is there any basic allocation method followed by Keil compiler?
5. What are the disadvantages of using absolute memory accesses(using _at_ ) for xdata variables if I use 64K external RAM, and what is the burden on the 8051 core controller
6. What could be the maximum permissible code size of common area if I use code banking with 2 code banks? I dedicated 6150 bytes code for common area in my project. Is it justified?
7. I used optimization level 9 for my project compilation. What are the adverse effects on the 8051 core controller if I use this highest level? What are the advantages and disadvantages? With this level of optimization, my code size is 104Kbytes of total 128Kbytes.
8. Is there a maximum limit to the size of the memory allocated to a structure that is compiled by Keil? I am using structure variables which use 150 bytes of xdata space each. Can I use a single structure which uses this much memory space?
9. Datatype {long} is not being supported in my project. If I create a variable of type {long}, there are no errors in compilation. But, the system is not functioning / booting . Are there any limitations in using {long} type?
10. Will Keil compiler support Timer 2 interrupt usage, if I use Timer 2 interrupt in my project with 8052 processor?
11. What are the advantages and disadvantages for the 89C52X2 core controller if I use 6x clock speed of execution instead of default 12x speed
12. What could be the maximum code size of an individual function in a Keil-compiled project?
kindly advise.
If you increase a 11.0592 MHz frequency by 22.1184 MHz, you will end up at 33.1776 MHz - is that what you really mean?
"what is the adverse effect"
Is your hardware properly designed for higher-frequency operation - particularly with respect to EMC?
"we are doing lot of memory mapped devices"
Changing the clock frequency will obviously affect the memory timings...
Increasing the clock speed sounds very much like a "band-aid" approach - ie, it just covers up the symptoms, without actually addressing the underlying cause(s)...
It sounds like you have a fundamentally under-powered hardware platform and/or fundamentally oversized and/or inefficient software
Remember, the 8051 is basically a simple architecture designed for no more than 64K of code...