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Why do we use only R0 & R1 in case of Indirect Addressing mode and why not any other GP registers? Can we use R0 & R1 of any bank or only Bank 0?
Thanks for your time and the answers Mr Andy.I am now convinced that only R0 & R1 can be used.But why did the chip manufacturers went for only the 1st two registers of any bank?someone told me it is because internally the MC executes certain jump instructions to move to the addresses of the particular registers to fetch their contents.And since R0 & R1 are the 1st two registers of any bank, the number of machine cycles is reduced incase we jump to R0/R1 and not any other registers,in which case time required to reach them will be more.Is it the case???please guide me!!
An 8-bit processor has very short instructions. A single byte can hold 256 values.
As Andy noted, the instruction uses 1 bit to select R0 or R1.
A processor with very few instructions can use more bits to select registers. A processor with many different instructions has fewer bits available for registers.
One of the reasons for the register banks is that it allows the processor to get a lot more registers without consuming extra bits in all instructions. It is enough to add instructions to perform the bank switch.
A 32-bit processor could have implemented 32 or 64 general registers, and allowed the compiler and/or the developer to specify which registers that should be reserved for different interrupt functions, and which registers should be gp registers in the main program.
A 64-bit processor that has 64-bit base instruction size can support a huge number of registers and still have room for a 32-bit offset, i.e. a fixed-size instruction mov r43,[r12+r15+1000000000];
Besides the size of the instruction set, there is another difference. The C51 processor is an old processor, and the original releases had a very, very small number of transistors. This requires limitations in the instruction set. A more complex instruction decoding requires more transistors, i.e. larger silicon area and larger current consumption.
Modern C51 processors can contain a lot more transistors and still keep a small die size and a low power consumption. The added transistors has been used to pipeline the chip, allowing overlapping execution of multiple instructions.
"I am now convinced that only R0 & R1 can be used"
Reading the Instruction Set document should have convined you of that!
"But why did the chip manufacturers went for only the 1st two registers of any bank?"
It is the chip designer's prerogative to design the chip in whatever way seems best to them within their design constraints. We shall probably never know why - and we don't need to! All we need to know is the available instructions set - then get on and use it!
However, as previously noted, the 'i' from "Ri" is encoded into a single bit; so the only way to support more registers would be to add more opcodes - and the 8051 doesn't have any spare opcodes! [1] Either that, or the @Ri opcodes would have to be extended by an extra byte - which would make the processor more complex, and the code bigger & less efficient. And to what benefit?
"Is it the case???"
Sounds highly unlikely to me! By using a single bit, the processor can simply select one register or the other - no need for additional internal "jump" instructions!
"please guide me!!"
Why does it actually matter?
If you want to study the internal operation of the 8051, there are plenty of models of it available on the web - you would need to study them!
It really isn't an issue for discussion here, as it has nothing to do with Keil software tools!
[1] Actually, there is 1 spare opcode - if you want to design your own "extended" 8051 instruction set, that would be the place to start...