Why do we use only R0 & R1 in case of Indirect Addressing mode and why not any other GP registers? Can we use R0 & R1 of any bank or only Bank 0?
An 8-bit processor has very short instructions. A single byte can hold 256 values.
As Andy noted, the instruction uses 1 bit to select R0 or R1.
A processor with very few instructions can use more bits to select registers. A processor with many different instructions has fewer bits available for registers.
One of the reasons for the register banks is that it allows the processor to get a lot more registers without consuming extra bits in all instructions. It is enough to add instructions to perform the bank switch.
A 32-bit processor could have implemented 32 or 64 general registers, and allowed the compiler and/or the developer to specify which registers that should be reserved for different interrupt functions, and which registers should be gp registers in the main program.
A 64-bit processor that has 64-bit base instruction size can support a huge number of registers and still have room for a 32-bit offset, i.e. a fixed-size instruction mov r43,[r12+r15+1000000000];
Besides the size of the instruction set, there is another difference. The C51 processor is an old processor, and the original releases had a very, very small number of transistors. This requires limitations in the instruction set. A more complex instruction decoding requires more transistors, i.e. larger silicon area and larger current consumption.
Modern C51 processors can contain a lot more transistors and still keep a small die size and a low power consumption. The added transistors has been used to pipeline the chip, allowing overlapping execution of multiple instructions.