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RAM code solution and troubles

Mapping externe:
Code:EPROM 00000--01FFF
Code:RAM 12000--1FFFF
Data:RAM 02000--0F6FF

External logic manage the A16 line of RAM chip:
- A16=1 on falling edge of ALE
- A16=0 when RD or WR = 0

My code is stored in 2 I2C eeprom. The Boot code download it in upper RAM (A16 force to 1), then goes in automatic mode described before.

Every things seams ok (sumckeck test works...) BUT I have a very strange behaviour: one program (A prog) works and another one (B prog) doesn't work. The only difference between them is local variable of a function. The A prog has int myVar; and the B has int idata myVar;

My target is a C505CA from infineon and I use the small model. My internal ramsize is 256. I have check in detail the both M51 file the overlay of memory. It seams to be ok.

To be sure that A prog works correctly I need to check two things:
1) my hardware solution
2) why the affectation of idata in local variable generates troubles

Parents
  • Using WR to control A16 causes A16 to go low after WR goes low on the RAM chip, and that will violate the address setup to falling WR timing requirement of the RAM chip. It may work, but I wouldn't do this.

    Maybe you could do it the other way around, where a data access is assumed unless PSEN goes low. In other words, use PSEN to control A16. During bootload A16 will have to be forced to 0. Remember that you can't access any C variables in the usual data portion of this RAM chip during your bootload. The only problem here is that you may need a faster RAM chip, because the address will not be stable until PSEN goes low plus your logic delay.

Reply
  • Using WR to control A16 causes A16 to go low after WR goes low on the RAM chip, and that will violate the address setup to falling WR timing requirement of the RAM chip. It may work, but I wouldn't do this.

    Maybe you could do it the other way around, where a data access is assumed unless PSEN goes low. In other words, use PSEN to control A16. During bootload A16 will have to be forced to 0. Remember that you can't access any C variables in the usual data portion of this RAM chip during your bootload. The only problem here is that you may need a faster RAM chip, because the address will not be stable until PSEN goes low plus your logic delay.

Children
  • If you have ALE available, you can use a RS flip flop.

    Where:
    Q = A16
    R = ALE and /PSEN
    S = ALE and not /PSEN

    This will set the address line valid at the beginning of the cycle.

  • I use C505CA, 12MHz and RAM 70ns
    The WR pulse minimum time is 250ns with our RAM of 70ns, so what happens if address lines change during the WR pulse which is very large?

  • if we use PSEN as A16, the A16 line will change during the PSEN pulse when reading program code. What happens?

  • I don't understand because ALE and not PSEN/ are never true. Could you precize?

  • There is still a setup time violation, no matter how long the WR pulse is. You cannot expect this to work reliably.

  • You are still waiting for PSEN, no matter if you latch PSEN or decode it with combinatorial logic. This has no material effect on the timing which will be the sum of:

    1) logic (or flip-flop) delay from falling PSEN to A16
    2) RAM read delay from address in to data out
    3) CPU code fetch setup time
    4) trace delays

  • There is no problem here because it is a read operation, not a write operation.

    All you have to worry about is meeting the code fetch setup time of the CPU.

    For the RAM chip there is no setup time requirment from valid address to falling OE. There is no possibility of data corruption during a RD cycle, so the timing is less critical.

  • to resume:

    C505CA, 12MHz, RAM 70ns
    PSEN pulse = 125ns
    RD or WR pulse = 250ns

                     --------
            1-------|D      Q|------A16ram
    ALEc505--------o|CLK     |
                    |        |
    RD/and WR/c505--|CLR     |
                     --------
    
    If I understand everything, this solution works for "read code" and "read data", not for "write data".

    If I keep this solution and separate WR/c505 from WR/ram with a 50ns delay on the falling edge, does it work?

  • to resume:

    C505CA, 12MHz, RAM 70ns
    PSEN pulse = 125ns
    RD or WR pulse = 250ns
    A16=1 -> upper RAM is CODE
    A16=0 -> lower RAM is DATA
    Note: Code is written with A16 forced to 1

    
    OE/ram = RD/c505 and PSEN/c505
    WE/ram = WR/c505
    
                     --------
            1-------|D      Q|------A16ram
    ALEc505--------o|CLK     |
                    |        |
    RD/and WR/c505--|CLR     |
                     --------
    
    (CLK is falling edge of ALEc505)
    

    If I understand everything, this solution works for "read code" and "read data", not for "write data".

    If I keep this solution and separate WR/c505 from WE/ram with a 50ns delay on the falling edge, does it work?

  • to resume:

    C505CA, 12MHz, RAM 70ns
    PSEN pulse = 125ns
    RD or WR pulse = 250ns
    A16=1 -> upper RAM is CODE
    A16=0 -> lower RAM is DATA
    Note: Code is written with A16 forced to 1

    
    OE/ram = RD/c505 and PSEN/c505
    WE/ram = WR/c505
    
                     --------
            1-------|D      Q|------A16ram
    ALEc505--------o|CLK     |
                    |        |
    RD/and WR/c505--|CLR     |
                     --------
    
    (CLK is falling edge of ALEc505)
    

    If I understand everything, this solution works for "read code" and "read data", not for "write data".

    If I keep this solution and separate WR/c505 from WE/ram with a 50ns delay on the falling edge, does it work?

  • If you can delay WE on the RAM chip until after A16 is valid then you will be OK.

  • New solution:

    CLK12MHzsin----|>o---|>o--CLK12MHz
    
                  -----                -----
    ALE----------|D   Q|----ALEFF1----|D   Q|----ALEFF2
    CLK12MHz----o|CLK  |           ---|CLK  |
             |    -----            |   -----
             |_____________________|
    

    A16=0 : RAM data
    A16=1 : Code
    Boot program force A16=1 to write code stored in E2PROM. After code is written the A16 is automatic and the program jump into written code.

    ALEFF1____________
                      |
                    -----
                   | PRE | 
    PSEN/---|>o----|D   Q|-----A16
    ALEFF2--------o|CLK  |
                   |     |
                    -----
    

    Here is the timings I expected:
               _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _  
    CLK12MHz _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
               ___         ___         ___                     ___         ___
    ALE      _|   |_______|   |_______|   |___________________|   |_______|   |___
                 ___         ___         ___                     ___         ___
    ALEFF1   ___|   |_______|   |_______|   |___________________|   |_______|   |_
                   ___         ___         ___                     ___         ___
    ALEFF2   _____|   |_______|   |_______|   |___________________|   |_______|   
               _____       _____       _____________________________       _____
    PSEN/    _|     |_____|     |_____|                             |_____|     |_
             ___________________________________               ___________________
    RD/ or WR                                   |_____________|
             _________________________________                   _________________
    A16      ___|                             |_________________|
    
    

    Are you agree with this new properly design?

    Thank you for your help
    Yann

  • I did not examine your logic, but if it does produce the timing relationships shown in your diagram then this should work.

  • This might give you better worse case timing.

    ALE________________
                      |
                    -----
                   | CLR | 
    1--------------|D   Q|-----A16
    /PSEN2--------o|CLK  |
                   |     |
                    -----
    

  • Why???
    What is /PSEN2 ?
    timing ?