Mapping externe: Code:EPROM 00000--01FFF Code:RAM 12000--1FFFF Data:RAM 02000--0F6FF External logic manage the A16 line of RAM chip: - A16=1 on falling edge of ALE - A16=0 when RD or WR = 0 My code is stored in 2 I2C eeprom. The Boot code download it in upper RAM (A16 force to 1), then goes in automatic mode described before. Every things seams ok (sumckeck test works...) BUT I have a very strange behaviour: one program (A prog) works and another one (B prog) doesn't work. The only difference between them is local variable of a function. The A prog has int myVar; and the B has int idata myVar; My target is a C505CA from infineon and I use the small model. My internal ramsize is 256. I have check in detail the both M51 file the overlay of memory. It seams to be ok. To be sure that A prog works correctly I need to check two things: 1) my hardware solution 2) why the affectation of idata in local variable generates troubles
New solution:
CLK12MHzsin----|>o---|>o--CLK12MHz ----- ----- ALE----------|D Q|----ALEFF1----|D Q|----ALEFF2 CLK12MHz----o|CLK | ---|CLK | | ----- | ----- |_____________________|
ALEFF1____________ | ----- | PRE | PSEN/---|>o----|D Q|-----A16 ALEFF2--------o|CLK | | | -----
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CLK12MHz _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ ___ ___ ___ ___ ___ ALE _| |_______| |_______| |___________________| |_______| |___ ___ ___ ___ ___ ___ ALEFF1 ___| |_______| |_______| |___________________| |_______| |_ ___ ___ ___ ___ ___ ALEFF2 _____| |_______| |_______| |___________________| |_______| _____ _____ _____________________________ _____ PSEN/ _| |_____| |_____| |_____| |_ ___________________________________ ___________________ RD/ or WR |_____________| _________________________________ _________________ A16 ___| |_________________|
I did not examine your logic, but if it does produce the timing relationships shown in your diagram then this should work.
This might give you better worse case timing.
ALE________________ | ----- | CLR | 1--------------|D Q|-----A16 /PSEN2--------o|CLK | | | -----
Why??? What is /PSEN2 ? timing ?
It was a typing error. /PSEN2 => /PSEN. For a data cycle, A16 is valid right after ALE is asserted. For a code cycle, A16 is valid right after /PSEN is asserted. In this design, "A16 stable" to the "leading edge of /WR" time is from the very beginning of the write cycle. In this design, "A16 stable" to the "micro reads data" time is from the very beginning of the read cycle. In this design, "A16 stable" to the "micro reads program" time is from the very beginning of "/PSEN" strobe.
For me your design is equivalent to:
A16 = not(PSEN/)