Mapping externe: Code:EPROM 00000--01FFF Code:RAM 12000--1FFFF Data:RAM 02000--0F6FF External logic manage the A16 line of RAM chip: - A16=1 on falling edge of ALE - A16=0 when RD or WR = 0 My code is stored in 2 I2C eeprom. The Boot code download it in upper RAM (A16 force to 1), then goes in automatic mode described before. Every things seams ok (sumckeck test works...) BUT I have a very strange behaviour: one program (A prog) works and another one (B prog) doesn't work. The only difference between them is local variable of a function. The A prog has int myVar; and the B has int idata myVar; My target is a C505CA from infineon and I use the small model. My internal ramsize is 256. I have check in detail the both M51 file the overlay of memory. It seams to be ok. To be sure that A prog works correctly I need to check two things: 1) my hardware solution 2) why the affectation of idata in local variable generates troubles
If you have ALE available, you can use a RS flip flop. Where: Q = A16 R = ALE and /PSEN S = ALE and not /PSEN This will set the address line valid at the beginning of the cycle.
I don't understand because ALE and not PSEN/ are never true. Could you precize?
You are still waiting for PSEN, no matter if you latch PSEN or decode it with combinatorial logic. This has no material effect on the timing which will be the sum of: 1) logic (or flip-flop) delay from falling PSEN to A16 2) RAM read delay from address in to data out 3) CPU code fetch setup time 4) trace delays