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RAM code solution and troubles

Mapping externe:
Code:EPROM 00000--01FFF
Code:RAM 12000--1FFFF
Data:RAM 02000--0F6FF

External logic manage the A16 line of RAM chip:
- A16=1 on falling edge of ALE
- A16=0 when RD or WR = 0

My code is stored in 2 I2C eeprom. The Boot code download it in upper RAM (A16 force to 1), then goes in automatic mode described before.

Every things seams ok (sumckeck test works...) BUT I have a very strange behaviour: one program (A prog) works and another one (B prog) doesn't work. The only difference between them is local variable of a function. The A prog has int myVar; and the B has int idata myVar;

My target is a C505CA from infineon and I use the small model. My internal ramsize is 256. I have check in detail the both M51 file the overlay of memory. It seams to be ok.

To be sure that A prog works correctly I need to check two things:
1) my hardware solution
2) why the affectation of idata in local variable generates troubles

Parents
  • to resume:

    C505CA, 12MHz, RAM 70ns
    PSEN pulse = 125ns
    RD or WR pulse = 250ns

                     --------
            1-------|D      Q|------A16ram
    ALEc505--------o|CLK     |
                    |        |
    RD/and WR/c505--|CLR     |
                     --------
    
    If I understand everything, this solution works for "read code" and "read data", not for "write data".

    If I keep this solution and separate WR/c505 from WR/ram with a 50ns delay on the falling edge, does it work?

Reply
  • to resume:

    C505CA, 12MHz, RAM 70ns
    PSEN pulse = 125ns
    RD or WR pulse = 250ns

                     --------
            1-------|D      Q|------A16ram
    ALEc505--------o|CLK     |
                    |        |
    RD/and WR/c505--|CLR     |
                     --------
    
    If I understand everything, this solution works for "read code" and "read data", not for "write data".

    If I keep this solution and separate WR/c505 from WR/ram with a 50ns delay on the falling edge, does it work?

Children
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