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  • Answered

    GICv2's programming errors -- several LRs with same SGI but distinct CPUIDs 0

    • Generic Interrupt Controller (GIC)
    10235 views
    1 reply
    Latest over 7 years ago
    by Olivier Delande
  • Suggested Answer

    rd/wr Speculation on TZC400 controller 0

    • TrustZone
    • CoreLink TZC-400
    9831 views
    1 reply
    Latest over 7 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    AMBA AXI CACHE 0

    • AMBA
    • AXI
    • Cache
    16646 views
    3 replies
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    AXI4 Stream difference between Position Byte and Null Byte 0

    • AXI
    • AXI4
    15350 views
    1 reply
    Latest over 7 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    [Cortex M0] Number of clock cycles for LDR instruction 0

    • Cortex-M0
    • Cortex-M
    13195 views
    1 reply
    Latest over 7 years ago
    by WestfW
  • Suggested Answer

    RE: In read or write transaction in AXI.what happen if data transaction  is before address. 0

    • AXI3
    • AXI
    9774 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI-4 questions 0

    • AMBA
    • AXI
    • AXI4
    21276 views
    3 replies
    Latest over 7 years ago
    by parvez
  • Answered

    ARM cortex M4 0

    • Memory Management Unit (MMU)
    • Cortex-M
    • Cortex-M4
    • Linux
    12808 views
    5 replies
    Latest over 7 years ago
    by daith
  • Suggested Answer

    Transfer size in AMBA AXI +1

    • AMBA
    • AXI
    14570 views
    2 replies
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Building position independent binary 0

    • cortex-m4f
    • Cortex-M
    12138 views
    4 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    Does Aarch64 LDTR behave differently in secure vs non-secure? 0

    • AArch64
    • Memory Management Unit (MMU)
    • C
    9066 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    How to invalidate cache (NVIDIA Drive PX2, ARMv8) 0

    • Cache coherency
    • Memory Management Unit (MMU)
    13510 views
    8 replies
    Latest over 7 years ago
    by Emme92
  • Discussion

    Custom RTOS - general ideas veryfication

    • Cortex-M7
    • Cortex-M
    • STM32F
    9575 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    TRACEDATA Capture issues 0

    • FPGA
    • CoreSight Debug and Trace
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    13561 views
    7 replies
    Latest over 7 years ago
    by Dave Marples
  • Not Answered

    arm link scatter file 0

    • Arm Compiler
    7854 views
    2 replies
    Latest over 7 years ago
    by fkemb
  • Not Answered

    Ahb 0

    • AHB
    6867 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    GICv2 How to resolve Multiple Interrupt appearing on a CPU 0

    • CoreLink GIC-400
    • Generic Interrupt Controller (GIC)
    8712 views
    1 reply
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    c++ virtual function override problem 0

    • C
    9940 views
    2 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    Value of "__initial_sp" 0

    • Keil
    • uVision
    • Cortex-M
    • Cortex-M4
    • Arm Compiler 5
    8667 views
    3 replies
    Latest over 7 years ago
    by WestfW
  • Not Answered

    WRAP BOUNDARY IN hsize=0 0

    • AHB
    5933 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
<>
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