[Cortex M0] Number of clock cycles for LDR instruction

Hello,

I need to know the exact number of the clock cycles per each instruction in terms of the system clock frequency especially the "LDR" instruction

Here is the needed instruction: "LDR r3,[r1]" 

Note that r1 is an address in the timer peripheral which corresponds to the current timer value.

I found out that in this link: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/CHDCICDF.html

LDR instruction takes two cycles.

However, I measured the number of clock cycles taken in this instruction and i found that this instruction takes 2 clock cycles but not from system clock frequency. The 2 clock cycles are taken from the BUS clock frequency which the timer works by.

I have two questions for the sake of this behavior:

1- Is that normal that the LDR instruction takes the two clock cycles measured by the BUS frequency not the system clock frequency which the CPU works by ?

2- Is there a solid reference showing the number of clock cycles per instruction for ARM v6-M cortex M0 please ?

Thank you in advance.