Hi experts,
When I design the real time architecture, I want to get benchmark timing data for interrupt latency to understand the system performance.
So, I ask the chip manufacturer TI. But TI recommend me to post at ARM forum.
I search this question at forum and Technical Reference Manual, but I can not get the answer.
Could you have suggestion?
PS: The interrupt latency I mean is that from interrupt is triggered to the first instruction of the user’s ISR.
Thanks in advanced
I cannot find an explicit reference, but from searching, ~20 cycles seems to be the consensus.
Thanks for this information.