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How to get the max interrupt latency in Cortex-R4F

Yongheng Ai

Hi experts,

When I design the real time architecture, I want to get benchmark timing data for interrupt latency to understand the system performance.

So, I ask the chip manufacturer TI. But TI recommend me to post at ARM forum.

I search this question at forum and Technical Reference Manual, but I can not get the answer.

Could you have suggestion?

PS: The interrupt latency I mean is that from interrupt is triggered to the first instruction of the user’s ISR.

Thanks in advanced

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  • +1

    Apologies - I first misread your query as regarding Cortex-M4F. I have deleted that response.

    There is no specified maximum latency, as this will depend on what the processor is currently doing. In theory, it could be in a handler of another IRQ that never returns.

    It is usual for a Vector Interrupt Controller be implemented along side the processor to minimize latency, determining in hardware which IRQ is to be handled next.

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  • +1

    Apologies - I first misread your query as regarding Cortex-M4F. I have deleted that response.

    There is no specified maximum latency, as this will depend on what the processor is currently doing. In theory, it could be in a handler of another IRQ that never returns.

    It is usual for a Vector Interrupt Controller be implemented along side the processor to minimize latency, determining in hardware which IRQ is to be handled next.

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