Hi experts,
When I design the real time architecture, I want to get benchmark timing data for interrupt latency to understand the system performance.
So, I ask the chip manufacturer TI. But TI recommend me to post at ARM forum.
I search this question at forum and Technical Reference Manual, but I can not get the answer.
Could you have suggestion?
PS: The interrupt latency I mean is that from interrupt is triggered to the first instruction of the user’s ISR.
Thanks in advanced
Apologies - I first misread your query as regarding Cortex-M4F. I have deleted that response.
There is no specified maximum latency, as this will depend on what the processor is currently doing. In theory, it could be in a handler of another IRQ that never returns.
It is usual for a Vector Interrupt Controller be implemented along side the processor to minimize latency, determining in hardware which IRQ is to be handled next.
Hi Ronan,
Thanks for your reply.
I got your point.
But I still have a question: Where can I get the ideal latency cycles?
I cannot find an explicit reference, but from searching, ~20 cycles seems to be the consensus.
Thanks for this information.