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Cortex M1, Cortex R4 - comparison

Mullai Thiagu
Note: This was originally posted on 25th September 2009 at http://forums.arm.com

Hi all,

Iam studyng the features supported by Cortex M1 and Cortex R4 soft processors. I have created a table for this and there are some features which i could not find.... it would be helpful if you guys can fill the missing features
  • Note: This was originally posted on 25th September 2009 at http://forums.arm.com

    > Cortex R4 soft processors

    Hmm, Cortex R4 isn't a soft processor AFAIK - it's designed for ASIC silicon implementation.

    Cortex-M1 is designed for low gate count - it only supports the ARMv6M variant of the Thumb instruction set, has a very simple single issue pipeline, and no cache interface, and perhaps can run at 100MHz in a fast FPGA (not entirely sure, never used one).

    Cortex-R4 is designed for higher performance implementations in silicon - it supports ARM and Thumb instruction sets (more suitable for algorithmic work), has a dual-issue pipeline (two instructions per cycle peak), and targets around 400MHz. A very different beast indeed. As ttfn says, if you want more details it's best too look at the two architecture documents - there are lots of differences!



    Thanks for the reply...I am basically interested in hardware related details....I have listed the features i want to compare for Cortex M1 and Cortex R4...

    It would be great if you guys can fill the details against each feature ...

    Thanks in advance


             Features    
                                            
    1. Primary FPGA Target
    2. Max Core Frequency
    3. FPGA Logic Cells
    4. Hardware Multipliers
    5. Hardware Dividers
    6. Instruction Cache Size
    7. Data Cache Size
    8. Number of ports for Instruction TCM / TCM-A (for Cortex R4)
    9. Number of ports for Data TCM / TCM-B (for Cortex R4)
    10. Burst Size Setting for Cache
    11. Exception Checking (Divsion error)
    12. MPU present/absent
    13. MMU present/absent
    14. Maximum number of Interrupts supported
    15. Options to select JTAG debug level - present/absent
    16. Option to set Custom instructions - present/absent
    17. Option to Set memory for Exception Vector - present/absent
    18. Is a separate FPGA kit (evaluation version) available for Cyclone III FPGA
    19. If Yes, does the kit consist of:
         Soft Core
         Software development environment
         Simulation support (for full version)
    20. Tool for Software development
    21. AMBA Bus Support - present/absent

  • Features    
                                            
    1. Primary FPGA Target
    Cortex-M1 deliverables supports Altera, Actel, Xilinx FPGA (for licensed customers).
    Current available FPGA kits include Altera version and Actel version.

    Cortex-R4 does not have FPGA kit as a product, but ARM customers can get FPGA prototype platform for Cortex-R4.

    2. Max Core Frequency

    Cortex-M1 : It depends : What FPGA? Which tools? Altera web site say using Cyclone III speed grade -6 you can get over 100MHz.  Internal testing done shown it can operate at over 180MHz
    You can get even higher speed if you are using newer Stratrix / Virtex devices.

    Cortex-R4 : It is not optimized for FPGA.  For ASIC version you can get it to 600MHz with hardened version (Cortex-R4X)

    3. FPGA Logic Cells

    Cortex-M1:This depends on RTL options, it shown as 2600 Logic elements in Altera website

    4. Hardware Multipliers
    Cortex-M1 : Yes
    Cortex-R4 : Yes

    5. Hardware Dividers
    Cortex-M1 : No
    Cortex-R4 : Yes

    6. Instruction Cache Size
    Cortex-M1 : No cache, TCM only (up to 1MB).
    Cortex-R4 : Depends on configuration, TCM also depends on configuration

    7. Data Cache Size
    Cortex-M1 : No cache, TCM only (up to 1MB)
    Cortex-R4 : Depends on configuration, TCM also depends on configuration

    8. Number of ports for Instruction TCM / TCM-A (for Cortex R4)
    64-bit TCM interface

    9. Number of ports for Data TCM / TCM-B (for Cortex R4)
    2 x 64-bit TCM interface

    10. Burst Size Setting for Cache
    Cortex-R4 : Programmable by CP15

    11. Exception Checking (Divsion error)
    Cortex-R4 : Yes

    12. MPU present/absent
    Cortex-M1 : No
    Cortex-R4 : Yes

    13. MMU present/absent
    Cortex-M1 : No
    Cortex-R4 : No

    14. Maximum number of Interrupts supported
    Cortex-M1 : 32
    Cortex-R4 : Depends on interrupt controller

    15. Options to select JTAG debug level - present/absent
    Cortex-M1 : Depends on which FPGA development you are using (e.g. with SOPC builder debug is carried out via the USB blaster connection)
    Cortex-R4 : Depends on which debug port component you connected it to.

    16. Option to set Custom instructions - present/absent
    Cortex-M1 : No
    Cortex-R4 : No

    17. Option to Set memory for Exception Vector - present/absent
    Cortex-M1 :Vector table at address 0x0 (can be AHB or TCM)
    Cortex-R4 : Vector table at address 0x0 or VIC interface

    18. Is a separate FPGA kit (evaluation version) available for Cyclone III FPGA
    Cortex-M1 only : FPGA kit available (not sure about evaluation)

    19. If Yes, does the kit consist of:
    Cortex-M1 only
         Soft Core : Yes
         Software development environment : Yes
         Simulation support (for full version) : You need to get ask distributor about this

    20. Tool for Software development
    Cortex-M1 kit include ARM RealView Microcontroller Development Kit

    21. AMBA Bus Support - present/absent
    Cortex-M1 for Actel use AMBA
    Cortex-M1 for Altera use Avalon
    Cortex-R4 use AMBA (AXI)

    Hi Joseph,

      thanks for ur reply.. it was really informative...

      Let me elaborate some more on my requirement...

    I need to build a system using Cortex M1 with AMBA bus in Altera tool. Next, i need to connect some peripherals like UART to AMBA bus.

    In this regard, it would be helpful if some one can provide clarification for queries below:

    1. Cortex M1 is available from ARM / as Cortex FPGA Evaluation Kit (from Arrow). Is this correct?

    2. How to get AMBA bus core components like AHB, APB and AHB-to-APB bridge ?

    3. I saw AMBA Design Kit and AMBA Designer tools provided by ARM. These are on-chip fabric for SoC systems. Is it possible to use AMBA Design kit (ADK) and generate AHB, APB and AHB-to-APB bridge components for Altera FPGAs?

    4. What is the difference between AMBA Design Kit(ADK) and AMBA Designer tools?

    5. Which of above tool (ADK / AMBA Designer ) can be used for generating AMBA components compatible with Cortex M1 processor to integrate and test systems in FPGA?

    6. Like Cortex M1 evaluation version, is there any evaluation version to use ADK / AMBA Designer ? If yes please give links for the same.


    Thanks in advance for the valuable informations you will share
  • Arm Employee Badge
    Note: This was originally posted on 25th September 2009 at http://forums.arm.com

    > Cortex R4 soft processors

    Hmm, Cortex R4 isn't a soft processor AFAIK - it's designed for ASIC silicon implementation.

    Cortex-M1 is designed for low gate count - it only supports the ARMv6M variant of the Thumb instruction set, has a very simple single issue pipeline, and no cache interface, and perhaps can run at 100MHz in a fast FPGA (not entirely sure, never used one).

    Cortex-R4 is designed for higher performance implementations in silicon - it supports ARM and Thumb instruction sets (more suitable for algorithmic work), has a dual-issue pipeline (two instructions per cycle peak), and targets around 400MHz. A very different beast indeed. As ttfn says, if you want more details it's best too look at the two architecture documents - there are lots of differences!
  • Arm Employee Badge
    Note: This was originally posted on 25th September 2009 at http://forums.arm.com

    Might be better to post the text.  As, I at least, always have certain amount of doubt over downloading/openning .doc files from unknown sources. Just a thought.

    Number 1 difference is the architecture they implement R4=v7-R  VS M1=v6-M.  Most of the programmer visible differences between the two cores comes from the architecture they implement.
  • Note: This was originally posted on 7th October 2009 at http://forums.arm.com

    1. Cortex M1 is available from ARM / as Cortex FPGA Evaluation Kit (from Arrow). Is this correct?

    Cortex-M1 is available from
    - ARM (IP licensing)
    - Altera (via SOPC builder)
    - Actel (via SoftConsole)
    - Synplicity (via ReadyIP program)


    2. How to get AMBA bus core components like AHB, APB and AHB-to-APB bridge ?

    If you are going to use Altera SOPC builder, the bus interface will be Avalon
    (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf)
    SOPC builder already come with some peripherals and required bus components.

    If you are using Actel tools, the development kit included a number of AMBA components.

    3. I saw AMBA Design Kit and AMBA Designer tools provided by ARM. These are on-chip fabric for SoC systems. Is it possible to use AMBA Design kit (ADK) and generate AHB, APB and AHB-to-APB bridge components for Altera FPGAs?

    If you are using SOPC builder, you need Avalon bus components.  Or if you license Cortex-M1 verilog source and ADK from ARM, you can integrate the components together by verilog coding.

    4. What is the difference between AMBA Design Kit(ADK) and AMBA Designer tools?

    ADK is a collection of AMBA components, with example testbench and scripts support for simulation and verification. ADK does not include AXI components.

    AMBA designer is a much more comprehensive tool with generation of system via GUI and supprt AXI.
    http://www.arm.com/products/solutions/AMBA_Designer.html

    5. Which of above tool (ADK / AMBA Designer ) can be used for generating AMBA components compatible with Cortex M1 processor to integrate and test systems in FPGA?

    Again, this depends on which design environment you are using.  If you are using SOPC builder you can generate your system without using individual AMBA components.  If you are using Actel Libero it has got AMBA components in its components library.


    6. Like Cortex M1 evaluation version, is there any evaluation version to use ADK / AMBA Designer ? If yes please give links for the same.

    You might find the following links useful:
    http://www.altera.com/education/demonstrations/sopc-builder/sopc-builder-demo.html
    http://www.actel.com/products/mpu/cortexm1/default.aspx
    http://www.actel.com/products/software/default.aspx
    http://www.synopsys.com/tools/implementation/fpgaimplementation/fpgasynthesis/pages/synplifypremier.aspx

    Ideally, you should contact Arrow/Altera/Actel to see what are their latest products.
    They might have lots of new stuffs coming out that we don't know :-)
  • Features    
                                            
    1. Primary FPGA Target
    Cortex-M1 deliverables supports Altera, Actel, Xilinx FPGA (for licensed customers).
    Current available FPGA kits include Altera version and Actel version.

    Cortex-R4 does not have FPGA kit as a product, but ARM customers can get FPGA prototype platform for Cortex-R4.

    2. Max Core Frequency

    Cortex-M1 : It depends : What FPGA?
    You can get even higher speed if you are using newer Stratrix / Virtex devices.

    Cortex-R4 : It is not optimized for FPGA.  For ASIC version you can get it to 600MHz with hardened version (Cortex-R4X)

    3. FPGA Logic Cells

    Cortex-M1:This depends on RTL options, it shown as 2600 Logic elements in Altera website

    4. Hardware Multipliers
    Cortex-M1 : Yes
    Cortex-R4 : Yes

    5. Hardware Dividers
    Cortex-M1 : No
    Cortex-R4 : Yes

    6. Instruction Cache Size
    Cortex-M1 : No cache, TCM only (up to 1MB).
    Cortex-R4 : Depends on configuration, TCM also depends on configuration

    7. Data Cache Size
    Cortex-M1 : No cache, TCM only (up to 1MB)
    Cortex-R4 : Depends on configuration, TCM also depends on configuration

    8. Number of ports for Instruction TCM / TCM-A (for Cortex R4)
    64-bit TCM interface

    9. Number of ports for Data TCM / TCM-B (for Cortex R4)
    2 x 64-bit TCM interface

    10. Burst Size Setting for Cache
    Cortex-R4 : Programmable by CP15

    11. Exception Checking (Divsion error)
    Cortex-R4 : Yes

    12. MPU present/absent
    Cortex-M1 : No
    Cortex-R4 : Yes

    13. MMU present/absent
    Cortex-M1 : No
    Cortex-R4 : No

    14. Maximum number of Interrupts supported
    Cortex-M1 : 32
    Cortex-R4 : Depends on interrupt controller

    15. Options to select JTAG debug level - present/absent
    Cortex-M1 : Depends on which FPGA development you are using (e.g. with SOPC builder debug is carried out via the USB blaster connection)
    Cortex-R4 : Depends on which debug port component you connected it to.

    16. Option to set Custom instructions - present/absent
    Cortex-M1 : No
    Cortex-R4 : No

    17. Option to Set memory for Exception Vector - present/absent
    Cortex-M1 :Vector table at address 0x0 (can be AHB or TCM)
    Cortex-R4 : Vector table at address 0x0 or VIC interface

    18. Is a separate FPGA kit (evaluation version) available for Cyclone III FPGA
    Cortex-M1 only : FPGA kit available (not sure about evaluation)

    19. If Yes, does the kit consist of:
    Cortex-M1 only
         Soft Core : Yes
         Software development environment : Yes
         Simulation support (for full version) : You need to get ask distributor about this

    20. Tool for Software development
    Cortex-M1 kit include ARM RealView Microcontroller Development Kit

    21. AMBA Bus Support - present/absent
    Cortex-M1 for Actel use AMBA
    Cortex-M1 for Altera use Avalon
    Cortex-R4 use AMBA (AXI)