This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex M1, Cortex R4 - comparison

Note: This was originally posted on 25th September 2009 at http://forums.arm.com

Hi all,

Iam studyng the features supported by Cortex M1 and Cortex R4 soft processors. I have created a table for this and there are some features which i could not find.... it would be helpful if you guys can fill the missing features
Parents
  • Note: This was originally posted on 25th September 2009 at http://forums.arm.com

    > Cortex R4 soft processors

    Hmm, Cortex R4 isn't a soft processor AFAIK - it's designed for ASIC silicon implementation.

    Cortex-M1 is designed for low gate count - it only supports the ARMv6M variant of the Thumb instruction set, has a very simple single issue pipeline, and no cache interface, and perhaps can run at 100MHz in a fast FPGA (not entirely sure, never used one).

    Cortex-R4 is designed for higher performance implementations in silicon - it supports ARM and Thumb instruction sets (more suitable for algorithmic work), has a dual-issue pipeline (two instructions per cycle peak), and targets around 400MHz. A very different beast indeed. As ttfn says, if you want more details it's best too look at the two architecture documents - there are lots of differences!
Reply
  • Note: This was originally posted on 25th September 2009 at http://forums.arm.com

    > Cortex R4 soft processors

    Hmm, Cortex R4 isn't a soft processor AFAIK - it's designed for ASIC silicon implementation.

    Cortex-M1 is designed for low gate count - it only supports the ARMv6M variant of the Thumb instruction set, has a very simple single issue pipeline, and no cache interface, and perhaps can run at 100MHz in a fast FPGA (not entirely sure, never used one).

    Cortex-R4 is designed for higher performance implementations in silicon - it supports ARM and Thumb instruction sets (more suitable for algorithmic work), has a dual-issue pipeline (two instructions per cycle peak), and targets around 400MHz. A very different beast indeed. As ttfn says, if you want more details it's best too look at the two architecture documents - there are lots of differences!
Children
No data