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ARM7 totally RISC?

lesbattersbie lesbattersbie
Note: This was originally posted on 9th May 2009 at http://forums.arm.com

Hi,

The ARM7 design does not follow the RISC features exactly and I understand this for most features except...
...with the size of the register bank.

I mean, what would be the consequence of changing the ARM7 register bank (16 registers) for a larger register bank with 32 registers?
  • Note: This was originally posted on 12th May 2009 at http://forums.arm.com

    Hi thanks for your reply!!

    [font="Tahoma"]would impact operand encoding, either forcing the removal of condition code per instruction or inline shifted operands within the ARM7
    hth
    s.[/font]


    Why would this be a result of having more registers?
  • Arm Employee Badge
    Note: This was originally posted on 12th May 2009 at http://forums.arm.com

    If you have more registers you need more bits to encode source and destination registers in the instructions... unless you increase instruction length you have to remove something to make space. You can encode a register selection from a bank 16 registers in 4 bits of instruction space - but 32 registers would need 5 bits. If you have a typical ARM instruction with one destination and two source registers you need to free up 3 additional bits of instruction space - it wouldn't be an ARM then of course =)
  • Arm Employee Badge
    Note: This was originally posted on 9th May 2009 at http://forums.arm.com

    [font="Tahoma"]I'm not quite sure what "the RISC features" are; anyway, increasing the number of registers to 32 would impact operand encoding, either forcing the removal of condition code per instruction or inline shifted operands within the ARM7. In addition, doubling the number of general purpose registers, whilst potentially making the compiler's register allocation simpler, would increase area + power and potentially impact the maximum achievable frequency.

    hth
    s.[/font]