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ARM7 totally RISC?

lesbattersbie lesbattersbie
Note: This was originally posted on 9th May 2009 at http://forums.arm.com

Hi,

The ARM7 design does not follow the RISC features exactly and I understand this for most features except...
...with the size of the register bank.

I mean, what would be the consequence of changing the ARM7 register bank (16 registers) for a larger register bank with 32 registers?
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  • Arm Employee Badge
    Note: This was originally posted on 12th May 2009 at http://forums.arm.com

    If you have more registers you need more bits to encode source and destination registers in the instructions... unless you increase instruction length you have to remove something to make space. You can encode a register selection from a bank 16 registers in 4 bits of instruction space - but 32 registers would need 5 bits. If you have a typical ARM instruction with one destination and two source registers you need to free up 3 additional bits of instruction space - it wouldn't be an ARM then of course =)
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  • Arm Employee Badge
    Note: This was originally posted on 12th May 2009 at http://forums.arm.com

    If you have more registers you need more bits to encode source and destination registers in the instructions... unless you increase instruction length you have to remove something to make space. You can encode a register selection from a bank 16 registers in 4 bits of instruction space - but 32 registers would need 5 bits. If you have a typical ARM instruction with one destination and two source registers you need to free up 3 additional bits of instruction space - it wouldn't be an ARM then of course =)
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