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ARM7 totally RISC?

lesbattersbie lesbattersbie
Note: This was originally posted on 9th May 2009 at http://forums.arm.com

Hi,

The ARM7 design does not follow the RISC features exactly and I understand this for most features except...
...with the size of the register bank.

I mean, what would be the consequence of changing the ARM7 register bank (16 registers) for a larger register bank with 32 registers?
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  • Arm Employee Badge
    Note: This was originally posted on 9th May 2009 at http://forums.arm.com

    [font="Tahoma"]I'm not quite sure what "the RISC features" are; anyway, increasing the number of registers to 32 would impact operand encoding, either forcing the removal of condition code per instruction or inline shifted operands within the ARM7. In addition, doubling the number of general purpose registers, whilst potentially making the compiler's register allocation simpler, would increase area + power and potentially impact the maximum achievable frequency.

    hth
    s.[/font]
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  • Arm Employee Badge
    Note: This was originally posted on 9th May 2009 at http://forums.arm.com

    [font="Tahoma"]I'm not quite sure what "the RISC features" are; anyway, increasing the number of registers to 32 would impact operand encoding, either forcing the removal of condition code per instruction or inline shifted operands within the ARM7. In addition, doubling the number of general purpose registers, whilst potentially making the compiler's register allocation simpler, would increase area + power and potentially impact the maximum achievable frequency.

    hth
    s.[/font]
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