I want to get acquainted with the M85 architecture, but I have a problem launching the model. When I want to run the Vio example it displays an error: Cannot find device cpu0.cpu0.l1dcachecom.arm.debug.dtsl.DTSLException: com.arm.debug.dtsl.DTSLException: Cannot find device cpu0.cpu0.l1dcacheCannot find device cpu0.cpu0.l1dcacheCannot find device cpu0.cpu0.l1dcache
I'm trying to run a model: Corstone SSE-310 Ethos-55 (MPS3).Can you help, please?
To measure the runtime performance of your M-class code on real hardware, you can count cycles using the Cortex-M's built-in memory-mapped DWT performance counters such as DWT_CYCCNT, or use the SysTick Timer, or use Streamline bare-metal profiling.See also Knowledge Base Article "Measuring the cycle count of the Cortex-M3 and Cortex-M4 processor's own activity" at:developer.arm.com/.../latestUnfortunately the Cortex-M FVP's do not model the DWT, but you can count instructions as shown in the FVP model's simulated LCD display, or (for larger functions) use the SysTick Timer.For real hardware, you can read DWT_CYCCNT at the start and at the end of the block of code of interest, then calculating the difference between the two values. This can be done either programmatically within your code (DWT_CYCCNT is a memory-mapped register at 0xE0001004) or by using the debugger to read DWT_CYCCNT at two breakpoints.Streamline bare-metal profiling is more complex to set up and requires you to write support code, but can give overall system level profiling information for larger code bases. See:developer.arm.com/.../Profiling-with-the-bare-metal-agentIf you need more information on this, I recommend you raise an official support case from the support menu above.Stephen