Cannot find device issue

Hi

My name is Stephen and I work at Arm.

Which version of models are you using?  The latest 11.24 version of the FVP_Corstone_SSE-310 models do not have an "cpu0.cpu0.l1dcache" parameter, so I think you will need to remove that.

You can view the available parameters with, e.g.
FVP_Corstone_SSE-310_Ethos-U65 --list-params

Which toolkit are you using to build and run the example, for example, Arm Development Studio, or Keil MDK?
Also, how are you launching the model?  Are you specifying model parameters (such as "cpu0.cpu0.l1dcache") explicitly in the GUI or are they embedded in a launcher script?  Feel free to send a screenshot if you need more help.

If you are using Arm Development Studio, there are some basic ready-made Cortex-M85 examples that work out-of-the-box to help you get started.  They are named "Cortex-M85" and "RTX5_Cortex-M85_Blinky".

To import these examples into your workspace:

1. Launch Arm Development Studio
2. Select File > Import... to open the Import Selection dialog
3. Expand the Arm Development Studio group and select Examples and Programming Libraries. Click Next
4. Expand the Examples group to view the example categories.
5. Either select one (or more) of the example categories to import, or expand the example categories to view/select individual examples in each category.  You can also enter a name (e.g. "M55") into the filter.
6. Click Finish to import the selected examples into your workspace.

For instructions on how to run and debug the examples, please see their readme.html files.

Hope this helps

Stephen

Thanks for letting us know that the "Cortex-M85" example works for you :)

You asked about performance.

developer.arm.com/.../Cortex-M85

gives the performance of Cortex-M85 as 6.28 CoreMark/MHz* and 3.13/4.52/8.76 DMIPS/MHz**

* Contact Arm for compilation conditions, as well as implementation data.
** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone. Arm Compiler 6.18.

To measure the runtime performance of your M-class code on real hardware, you can count cycles using the Cortex-M's built-in memory-mapped DWT performance counters such as DWT_CYCCNT, or use the SysTick Timer, or use Streamline bare-metal profiling.

See also Knowledge Base Article "Measuring the cycle count of the Cortex-M3 and Cortex-M4 processor's own activity" at:

developer.arm.com/.../latest

Unfortunately the Cortex-M FVP's do not model the DWT, but you can count instructions as shown in the FVP model's simulated LCD display, or (for larger functions) use the SysTick Timer.

For real hardware, you can read DWT_CYCCNT at the start and at the end of the block of code of interest, then calculating the difference between the two values.  This can be done either programmatically within your code (DWT_CYCCNT is a memory-mapped register at 0xE0001004) or by using the debugger to read DWT_CYCCNT at two breakpoints.

Streamline bare-metal profiling is more complex to set up and requires you to write support code, but can give overall system level profiling information for larger code bases.  See:

developer.arm.com/.../Profiling-with-the-bare-metal-agent

If you need more information on this, I recommend you raise an official support case from the support menu above.

Stephen