Hello
I want to get acquainted with the M85 architecture, but I have a problem launching the model. When I want to run the Vio example it displays an error: Cannot find device cpu0.cpu0.l1dcachecom.arm.debug.dtsl.DTSLException: com.arm.debug.dtsl.DTSLException: Cannot find device cpu0.cpu0.l1dcacheCannot find device cpu0.cpu0.l1dcacheCannot find device cpu0.cpu0.l1dcache
I'm trying to run a model: Corstone SSE-310 Ethos-55 (MPS3).Can you help, please?
HiMy name is Stephen and I work at Arm.Which version of models are you using? The latest 11.24 version of the FVP_Corstone_SSE-310 models do not have an "cpu0.cpu0.l1dcache" parameter, so I think you will need to remove that.You can view the available parameters with, e.g.FVP_Corstone_SSE-310_Ethos-U65 --list-paramsWhich toolkit are you using to build and run the example, for example, Arm Development Studio, or Keil MDK?Also, how are you launching the model? Are you specifying model parameters (such as "cpu0.cpu0.l1dcache") explicitly in the GUI or are they embedded in a launcher script? Feel free to send a screenshot if you need more help.If you are using Arm Development Studio, there are some basic ready-made Cortex-M85 examples that work out-of-the-box to help you get started. They are named "Cortex-M85" and "RTX5_Cortex-M85_Blinky".To import these examples into your workspace:
For instructions on how to run and debug the examples, please see their readme.html files.Hope this helpsStephen
HiThanks for the answer, the simulation model for the example "Cortex-M85" works.I apologize for the offtopic question.How to measure MCPS for M85?Thanks
Thanks for letting us know that the "Cortex-M85" example works for you :)You asked about performance.developer.arm.com/.../Cortex-M85gives the performance of Cortex-M85 as 6.28 CoreMark/MHz* and 3.13/4.52/8.76 DMIPS/MHz*** Contact Arm for compilation conditions, as well as implementation data.** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone. Arm Compiler 6.18.
Sorry, but I cannot find how to measure and print cycle-counts for function.Can you please help?
To measure the runtime performance of your M-class code on real hardware, you can count cycles using the Cortex-M's built-in memory-mapped DWT performance counters such as DWT_CYCCNT, or use the SysTick Timer, or use Streamline bare-metal profiling.See also Knowledge Base Article "Measuring the cycle count of the Cortex-M3 and Cortex-M4 processor's own activity" at:developer.arm.com/.../latestUnfortunately the Cortex-M FVP's do not model the DWT, but you can count instructions as shown in the FVP model's simulated LCD display, or (for larger functions) use the SysTick Timer.For real hardware, you can read DWT_CYCCNT at the start and at the end of the block of code of interest, then calculating the difference between the two values. This can be done either programmatically within your code (DWT_CYCCNT is a memory-mapped register at 0xE0001004) or by using the debugger to read DWT_CYCCNT at two breakpoints.Streamline bare-metal profiling is more complex to set up and requires you to write support code, but can give overall system level profiling information for larger code bases. See:developer.arm.com/.../Profiling-with-the-bare-metal-agentIf you need more information on this, I recommend you raise an official support case from the support menu above.Stephen