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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    Just a processor? 0

    3825 views
    4 replies
    Latest over 6 years ago
    by Marcelo Jayme Arm Employee Badge
  • Answered

    Memory Protection Unit - Complexity in usage +1

    9325 views
    7 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Monitor Mode Debug 0

    7381 views
    7 replies
    Latest over 6 years ago
    by Andy Neil
  • Answered

    32-bit encoding hex values for Arm instructions 0

    6124 views
    3 replies
    Latest over 6 years ago
    by BQL
  • Answered

    Cycle count for a subroutine on Cortex M33 0

    7962 views
    2 replies
    Latest over 6 years ago
    by Ed Player Arm Employee Badge
  • Answered

    TrustZone in CortexR +1

    • Cortex-R
    • virtualization
    • TrustZone
    9335 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Where to find hard core Arm books, courses, tutorials 0

    • Arm7tdmi
    10080 views
    6 replies
    Latest over 6 years ago
    by drake00
  • Suggested Answer

    arm1176jzf-s fiq context switch 0

    19535 views
    1 reply
    Latest over 6 years ago
    by Peter Rielly Arm Employee Badge
  • Not Answered

    A72 not handling IRQ properly 0

    • Cortex-A72
    • Interrupt Handling
    18628 views
    0 replies
    Started over 6 years ago
    by MNB
  • Answered

    Debug Unit Cortex - R 0

    6293 views
    3 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Cortex-M: Does the event register only get set when an IRQ changes from not pending to pending? 0

    • Interrupt Handling
    • event
    • Cortex-M4
    7410 views
    3 replies
    Latest over 6 years ago
    by m.wagner
  • Answered

    Is CPSR.F settable through debug port? (e.g. JTAG) +1

    • Cortex-R5
    • CPSR
    • Debugging
    5978 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Instruction Fault Generation +1

    5374 views
    2 replies
    Latest over 6 years ago
    by techguyz
  • Answered

    Disable data prefetching in a Cortex-A53 running Android +1

    • Cortex-A53
    • EL1
    • L1
    • L2
    26368 views
    6 replies
    Latest over 6 years ago
    by DNovo
  • Answered

    How to determine which core is generating the AXI read transaction in a multi core processor? 0

    • Cortex-A72
    21747 views
    3 replies
    Latest over 6 years ago
    by MNB
  • Answered

    ARM Cortex A5 -Issue: Undefined Instruction when write/read value of CNTFRQ register in core ARMv7 0

    20065 views
    2 replies
    Latest over 6 years ago
    by Khuong Nguyen
  • Not Answered

    Trigger a Software Interrupt 0

    • Cortex-M
    • Cortex-M4
    • Interrupt
    6264 views
    1 reply
    Latest over 6 years ago
    by Haiyan Arm Employee Badge
  • Answered

    "BX LR" causing INVPC Usage Fault exception 0

    • Cortex-M7
    • Microcontroller (MCU)
    • Arm Assembly Language (ASM)
    • Cortex-M7 FVP
    8519 views
    2 replies
    Latest over 6 years ago
    by Sohaib
  • Not Answered

    What is the behavior for a "BKPT" instruction in a HardFault handler 0

    20858 views
    4 replies
    Latest over 6 years ago
    by Brett Bergquist
  • Answered

    Page Table Indexing using Virtual Address bits +1

    20688 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
<>
Topics being discussed in this forum
  • AArch64
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