Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Answered

    Cortex-M0+ hangs on return 0

    • Cortex-M0+
    3676 views
    1 reply
    Latest over 6 years ago
    by trf
  • Answered

    Data Abort on read, although write can be executed without any abort. +1

    • Armv7 Exception Model
    • Memory
    7526 views
    3 replies
    Latest over 6 years ago
    by r4c00n
  • Answered

    Hypervisor for Arm Cortex A9 +1

    • Embedded Software
    • Arm9
    • Embedded Hypervisor
    • Hypervisor
    15622 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    FPU version for Cortex-M microcontrollers 0

    • Cortex-M
    3672 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    SWD for Time Profiling if no ETM Time Stamping is available +1

    • Profiling
    • Trace Debug Tools (TDT)
    • Debugger
    • Cortex-M4
    3217 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    SWD for Time Profiling if no ETM Time Stamping is available 0

    • Real-Time
    • Trace Debug Tools (TDT)
    • Debugging
    • Cortex-M4
    12898 views
    0 replies
    Started over 6 years ago
    by Andrea Bettati
  • Not Answered

    Non-secure code calling secure code - Boot Loaders 0

    10117 views
    2 replies
    Latest over 6 years ago
    by vinkot Arm Employee Badge
  • Answered

    Count Main TLB miss +1

    • Cortex-A9
    • performance analysis
    14811 views
    1 reply
    Latest over 6 years ago
    by Vanhealsing
  • Answered

    Interrupts in assembly language +1

    • Microcontroller (MCU)
    • Interrupt
    13848 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    The Peripherals memory map of FVP_BaseR_Cortex-R52x1 0

    • Cortex-R52
    • Fixed Virtual Platforms (FVPs)
    • PrimeCell UART (PL011)
    2547 views
    0 replies
    Started over 6 years ago
    by Jex1x
  • Answered

    Basic difference between "Generic User Guide" and "Technical Reference Manual" +1

    • Cortex-M0+
    16270 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    VMSAv8-64 and spinlock +1

    • Cortex-A53
    • Cache coherency
    • Cortex-A
    • Baremetal
    16639 views
    3 replies
    Latest over 6 years ago
    by Ciro Donnarumma
  • Answered

    A question aboout Monitor Vector Base Address Register(MVBAR) 0

    • Cortex-A9
    • TrustZone
    16782 views
    6 replies
    Latest over 6 years ago
    by scribnote5
  • Answered

    SysTick 0

    • 15 (SysTick)
    3663 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    shareable domain and cache policy problem 0

    • Cortex-A53
    • big.LITTLE
    • L1
    • Cache
    • Cortex-A
    • L2
    12638 views
    0 replies
    Started over 6 years ago
    by zhi
  • Answered

    Configuring an interrupt source as FIQ at EL1 +1

    • Cortex-A53
    • GICv2
    • Kernel Developers
    17067 views
    2 replies
    Latest over 6 years ago
    by Sumit Batra
  • Answered

    MMU initialization for an ARM multicore system +1

    • Cortex-A9
    • Memory Management Unit (MMU)
    • Cortex-A
    • Baremetal
    • Memory
    20596 views
    6 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Why NSCAR(Non-secure Access Control Register) changes often? 0

    • Cortex-A9
    • Registers
    • TrustZone
    14440 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    stm32f103c8t6 "blue pill" board +1

    • Cortex-M3
    • IDEs and Tool Suites
    • Cortex-M
    3772 views
    1 reply
    Latest over 6 years ago
    by chrisKConti
  • Not Answered

    NMI Handling in Bootloader +1

    • 2 (NMI)
    • Cortex-M
    4513 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone