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Relocating the Vector table in Cortex - M0

Prasad Kadam

Hi

I am having an issue,  related to vector table relocation in a Cortex - m0 based device, as VTOR isnt available there in this core, how can i manage the ISRs  in a application which is not at default flash address i.e. 0x8000000, i am able to jump from my boot loader code to the application code, but after interrupt generation code stops. need help thanks in advance

Prasad  

Parents
  • 0 Arm Employee Badge in reply to 42Bastian Schick

    That's right. Please see ST manual 0360:

    www.st.com/.../dm00091010.pdf

    Section 9.1.1 SYSCFG configuration register 1

    Bits 1:0 MEM_MODE[1:0]: Memory mapping selection bits
    These bits are set and cleared by software. They control the memory internal mapping at
    address 0x0000 0000. After reset these bits take on the value selected by the actual boot
    mode configuration. Refer to Chapter 2.5: Boot configuration for more details.
    x0: Main Flash memory mapped at 0x0000 0000
    01: System Flash memory mapped at 0x0000 0000
    11: Embedded SRAM mapped at 0x0000 0000

Reply
  • 0 Arm Employee Badge in reply to 42Bastian Schick

    That's right. Please see ST manual 0360:

    www.st.com/.../dm00091010.pdf

    Section 9.1.1 SYSCFG configuration register 1

    Bits 1:0 MEM_MODE[1:0]: Memory mapping selection bits
    These bits are set and cleared by software. They control the memory internal mapping at
    address 0x0000 0000. After reset these bits take on the value selected by the actual boot
    mode configuration. Refer to Chapter 2.5: Boot configuration for more details.
    x0: Main Flash memory mapped at 0x0000 0000
    01: System Flash memory mapped at 0x0000 0000
    11: Embedded SRAM mapped at 0x0000 0000

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