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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Answered

    Why does Cortex-R only support most two cores? 0

    • Cortex-R
    • Cortex-R5
    • Cortex-A
    • Cortex-R7
    4560 views
    2 replies
    Latest over 10 years ago
    by Jon Taylor Arm Employee Badge
  • Answered

    I want to know how to invalidate or clean to cache only used secure-world 0

    • big.LITTLE
    • Cache
    • Armv8-A
    11343 views
    6 replies
    Latest over 10 years ago
    by 박주병
  • Answered

    Thirdparty RTOS support for ARM V8 +1

    • Armv8-A
    • Armv8-R
    3387 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Programming ARMv8 memory mapped registers +1

    • APB
    6877 views
    5 replies
    Latest over 10 years ago
    by Ravinder
  • Answered

    Non aligned access in arm v7 going into exception 0

    • Cache
    9262 views
    3 replies
    Latest over 10 years ago
    by David Wang Arm Employee Badge
  • Answered

    ARM Cortex-A7 generic timer 0

    • Cortex-A
    • Cortex-A7
    11388 views
    4 replies
    Latest over 10 years ago
    by hostia
  • Answered

    Question about a code snippet on ARM, Thumb state change 0

    • Thumb
    9268 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Is the 'S' necessary in the asm code? 0

    • Cortex-A
    • Cortex-A8
    • C
    5419 views
    5 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    What does it mean 'IT can be omitted'? +1

    • Thumb
    • Cortex-A
    5860 views
    4 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Not Answered

    What type of ARM is used in 10-Gb Ethernet chip? 0

    • Cortex-A57
    • Cortex-A15
    • Cortex-A
    6255 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    How to understand SDIV instruction availability? 0

    • 32-bit
    • Armv7-A
    • Cortex-A15
    • Cortex-A
    • Thumb2
    6645 views
    2 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    How many states for an ARM Cortex A8? 0

    • Thumb
    • Cortex-A
    • Cortex-A8
    • Thumb2
    4923 views
    1 reply
    Latest over 10 years ago
    by daith
  • Answered

    What is P1, P2, P3 and P4 use in Thumb2 IF block instruction? 0

    • Thumb2
    7245 views
    1 reply
    Latest over 10 years ago
    by daith
  • Answered

    Why does ARMSim# not recognize instruction 'addw'? 0

    • Arm7
    • Thumb
    7058 views
    3 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Fastest way to transpose array in cortex-m4? +1

    • Cortex-M
    • Cortex-M4
    3303 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    indicator for A core system timer implemented or not 0

    • Armv7-A
    • AArch64
    • Armv8-A
    • Armv7-R
    • AArch32
    5769 views
    4 replies
    Latest over 10 years ago
    by hostia
  • Answered

    Cortex-A7 Processor DSP +1

    • Cortex-A
    • Cortex-A7
    6846 views
    5 replies
    Latest over 10 years ago
    by Акоб
  • Answered

    Why does ARM Branch with Link (BL) instruction considers prefetch? +1

    • Thumb
    5018 views
    1 reply
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    ARM Cortex A8 : Enabling D Cache aborts 0

    • Cache
    • Cortex-A
    • Cortex-A8
    59344 views
    32 replies
    Latest over 10 years ago
    by Gopu
  • Answered

    What's the difference between core, processor,cluster and CPU in ARM architecture? 0

    • Cortex-A15
    • Cortex-A
    • Cortex-M
    22577 views
    1 reply
    Latest over 10 years ago
    by Alban Rampon
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