Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Not Answered

    How to place FreeRTOS in secure memory and the user tasks in non-secure memory? 0

    • TrustZone
    • Armv8-M
    43238 views
    21 replies
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    how to understand L1 cache but L2 & L3 non-cached +1

    • L1
    • L3
    • Cortex-A55
    • Cache
    • Cortex-A
    • L2
    21501 views
    4 replies
    Latest over 6 years ago
    by phil9980
  • Answered

    Cortex R5 behavior when a masked imprecise/asynchronous abort occurs +1

    9691 views
    6 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    GICv3 Group0 secure interrupts routed to monitor when running in S-EL1 0

    • EL1
    • EL3
    • GICv3/v4
    • Interrupt
    16523 views
    2 replies
    Latest over 6 years ago
    by odeprez
  • Answered

    Modify SP register and PC register in Cortex-M1 using Keil 0

    • R15 (PC Program Counter)
    • Cortex-M1
    • R13 (SP Stack Pointer)
    • Keil
    5965 views
    4 replies
    Latest over 6 years ago
    by Juanea7
  • Answered

    MPIDR and affinity +1

    • AArch64
    18007 views
    2 replies
    Latest over 6 years ago
    by Soummya Mallick
  • Answered

    ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state? +1

    • Armv8-A
    • AArch32
    16539 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Watchdog timer not entering ISR 0

    • Cortex-A9
    • Interrupt Controller Devices
    • Cortex-A
    • Interrupt
    16433 views
    2 replies
    Latest over 6 years ago
    by sherry
  • Answered

    Binary Semaphore upset by FIQ +1

    • Cortex-A
    26144 views
    20 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Identifying Generic IP Components on an Access Port 0

    • Cortex-M0
    • Cortex-M
    • Debugger
    • CoreSight
    • Cortex-M4
    2221 views
    0 replies
    Started over 6 years ago
    by Torsten Robitzki
  • Not Answered

    Issue with WatchDog reset De-asserting 0

    • Cortex-A9
    • Cortex-A
    13371 views
    0 replies
    Started over 6 years ago
    by BAB
  • Not Answered

    Getting processor and cache details 0

    • Cache
    • Linux
    14085 views
    0 replies
    Started over 6 years ago
    by karthikeyan.d
  • Not Answered

    Loading cortex M1 soft processor on Pynq Processor 0

    • Cortex-M1
    • Cortex-M
    2616 views
    0 replies
    Started over 6 years ago
    by Sivasankar
  • Answered

    AXI4 Lite handshake +1

    • AMBA
    • AXI
    • Interface
    17073 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    AARCH64 banked registers +1

    • Cortex-A53
    • AArch64
    15956 views
    2 replies
    Latest over 6 years ago
    by LdB
  • Answered

    Cortex-A9 TLB lockdown +1

    • Cortex-A9
    14518 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    New developer guides for AArch64 +1

    • AArch64
    16370 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Beginner question: stack pointer initialization +1

    • Cortex-M
    10812 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Suggested Answer

    Cortex-A8: memcpy() into DMA buffer hangs on NEON instructions 0

    • DMA Devices
    • Cortex-A
    • Cortex-A8
    17048 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Boot sequence and secure boot 0

    • Cortex-M23
    • Cortex-M
    • Armv8-M
    13379 views
    2 replies
    Latest over 6 years ago
    by LukaP
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone