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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Answered

    AHB5 did'nt mention SPLIT and RETRY responses 0

    • AHB5
    10777 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Trace decompressor: Are barrier instructions and synchronization primitives really waypoints? +1

    • Trace
    • CoreSight Debug and Trace
    • CoreSight PTM-A9
    9586 views
    2 replies
    Latest over 6 years ago
    by Oddjob6
  • Suggested Answer

    Fundamental Doubt in AHB Bus Architecture 0

    • Protocols
    • SoC Implementation
    • Interface Bus Architecture
    • Microcontroller (MCU)
    • Networking Protocol
    • AHB-Lite
    9946 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    What is meant by a Master in the AHB-Lite specification? 0

    12022 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    How to select endianess in AHB? +1

    10105 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Number of byte count 0

    9711 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Help with porting Intel AVX to arm64 +1

    • AArch64
    • Arm64
    16525 views
    1 reply
    Latest over 6 years ago
    by jtzhou
  • Answered

    MMU - Permission Fault with EL1 access +1

    • Cortex-A53
    • AArch64
    • Raspberry Pi 3
    • Armv8-A
    • Memory Management Unit (MMU)
    16208 views
    3 replies
    Latest over 6 years ago
    by Dumitru
  • Answered

    Why is PC-relative addressing deprecated for STR and VSTR in ARMv7-M4? +1

    16340 views
    8 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Neoverse N1 CPU Questions +1

    12959 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped +1

    • Cortex-A9
    • CoreLink L2C-310 Level 2 Cache Controller
    • Memory Management Unit (MMU)
    • Cortex-A
    13109 views
    8 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    M0+ Stack Pointer (PSP/MSP) Clarification 0

    • Cortex-M0
    • Cortex-M3
    • Thumb
    • Cortex-M
    • Arm Assembly Language (ASM)
    • C
    17165 views
    15 replies
    Latest over 6 years ago
    by Sean Dunlevy
  • Answered

    ARMv8-A: Virtual to physical translation sometime "fails" 0

    • Armv8-A
    8400 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence 0

    • Cortex-A53
    • Cortex-R
    • CoreLink CCI-400 Cache Coherent Interconnect
    • Cache coherency
    • Cortex-R5
    • Cortex-A
    10505 views
    6 replies
    Latest over 6 years ago
    by Sandeep Bobba
  • Answered

    How to flush the pipeline of a processor using XScale-compatible Assembly? +1

    • Arm Development Studio
    • Cortex-A15
    • Cortex-A
    • Arm Assembly Language (ASM)
    10093 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Non-secure EXC_RETURN value to Secure HardFault Handler 0

    10495 views
    2 replies
    Latest over 6 years ago
    by Rajiv
  • Answered

    JTAG to TrustZone Cortex-M33 0

    • CHI
    • TrustZone
    • Armv8-M
    11648 views
    2 replies
    Latest over 6 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    ARM64: LDR (register) SXTX extend +1

    • AArch64
    • Arm64
    15252 views
    5 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Cortex-A5 and configuration for real time task +1

    • APB
    • Cortex-A5
    • Memory Management Unit (MMU)
    • Cortex-A
    • AHB
    11550 views
    4 replies
    Latest over 6 years ago
    by Vanhealsing
  • Not Answered

    DMIPS calculation for application software on ARM Cortex A7 0

    • Software
    • Application Software
    • Cortex-A7
    12561 views
    0 replies
    Started over 6 years ago
    by Sanjeev Kumar
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone