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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3594 Questions
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  • Answered

    Difference between thumb machine directives 0

    • Thumb
    12714 views
    3 replies
    Latest over 11 years ago
    by daith
  • Answered

    Use case of MSP and PSP in Cortex M 0

    48218 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    Cortex-M4 interrupt priority dynamically change while in ISR 0

    • Cortex-M4
    • Interrupt
    20122 views
    14 replies
    Latest over 11 years ago
    by Adnan Ashraf
  • Answered

    Recently i bought a new kit supporting cortex m0+ processor ! I read the complete datasheet but could not find the instruction for using GPIO !! 0

    • Cortex-M0+
    4102 views
    1 reply
    Latest over 11 years ago
    by Jens Bauer
  • Answered

    ASM instruction error 0

    • Cortex-A
    • Arm Assembly Language (ASM)
    9289 views
    5 replies
    Latest over 11 years ago
    by techguyz
  • Answered

    Is Cortex-A56 Maia or Artemis? 0

    • Armv8
    • 64-bit
    10259 views
    2 replies
    Latest over 11 years ago
    by wangyong
  • Answered

    Is the functionality of TZC400 working on ARMv8 FVP base model? +1

    • Corelink
    • Armv8
    • CoreLink TZC-400
    5264 views
    3 replies
    Latest over 11 years ago
    by SY Chiu
  • Answered

    Can a Linux kernel run as a TrustZone secure OS? +1

    • TrustZone
    • Interrupt
    16863 views
    6 replies
    Latest over 11 years ago
    by Sudeep Holla Arm Employee Badge
  • Answered

    Getting Started in Real-Time Applications 0

    • Real-Time
    6026 views
    4 replies
    Latest over 11 years ago
    by Alban Rampon
  • Answered

    Cryptography instructions sample for ARMv8 0

    • Armv8
    • Armv8-A
    5254 views
    1 reply
    Latest over 11 years ago
    by Sudeep Holla Arm Employee Badge
  • Answered

    ARM Cortex A8 - if IRQ interrupts are disabled in CPSR register While the processor is executing, system results in data abort. What might be the reason to trigger data abort +1

    • CPSR
    • Cortex-A
    • Cortex-A8
    • Processors
    • Interrupt
    5683 views
    1 reply
    Latest over 11 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    What happens if an interrupt occurs as it is already disabled +1

    • Armv7
    • Cortex-A
    • Cortex-A8
    • Interrupt
    10990 views
    2 replies
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Few beginner questions - from AVR to ARM 0

    • Raspberry Pi
    • Embedded
    34913 views
    28 replies
    Latest over 11 years ago
    by kamran
  • Answered

    Cortex-A7 4 Cores Boot +1

    • Cortex-A
    • Cortex-A7
    6538 views
    1 reply
    Latest over 11 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    WFE/WFI and pending interrupts? +1

    24407 views
    7 replies
    Latest over 11 years ago
    by Manyam
  • Answered

    How to build an application for dual core(M4+M0) MCU? 0

    • Cortex-M
    24548 views
    10 replies
    Latest over 11 years ago
    by Alban Rampon
  • Answered

    Cortex-M pipeline, relationship prefetch and decode stages 0

    • Pipeline Control and Execution
    • Cortex-M
    12214 views
    5 replies
    Latest over 11 years ago
    by Yasuhiko Koumoto
  • Answered

    Cortex-A8 : instruction fetch for dual-issue +1

    • Cortex-A8
    6332 views
    3 replies
    Latest over 11 years ago
    by Gang-Ryung Uh
  • Answered

    Could you tell me what the gate count of ARM926 is? 0

    • Arm926
    • Processors
    11313 views
    7 replies
    Latest over 11 years ago
    by Chris Shore
  • Answered

    I wrote a code for UART0 in LPC2148 for transmitting - it is working at debugging, but not working in proteos +1

    • Arm7
    • Debugging
    4505 views
    2 replies
    Latest over 11 years ago
    by Velagala J R N D V Reddy
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Topics being discussed in this forum
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