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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3632 Questions
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  • Not Answered

    Bootloader - Renesas RZA1H from Serial Flash 0

    11891 views
    0 replies
    Started over 7 years ago
    by KVK
  • Not Answered

    Explain 8 stage pipeline of ARM Cortex a7? 0

    • Pipeline Control and Execution
    • NEON
    • Cortex-A
    • Cortex-A7
    13321 views
    0 replies
    Started over 7 years ago
    by rakeshgp3
  • Answered

    The easiest way to debug a lockup reset on Cortex M7 +1

    • Cortex-M7
    • Debugger
    15786 views
    9 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    RFFT CMSIS-DSP - Fluctuating index +1

    • Digital Signal Processor (DSP)
    • Cortex-M
    • CMSIS
    • Cortex-M4
    4564 views
    1 reply
    Latest over 7 years ago
    by SweetPotato
  • Answered

    How many bits has TBLOFF in VTOR for Cortex M7? 0

    • Cortex-M7
    • Armv7 Exception Model
    • Interrupt
    5385 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    How to pass arguments to a bare-metal app using u-boot 0

    • U-Boot
    11523 views
    0 replies
    Started over 7 years ago
    by josecm
  • Not Answered

    Is it OK to bypass all clock gates in Cortex-R52? 0

    • Cortex-R52
    • Clocking Structures & Timing Mechanisms
    • SoC FPGA
    2718 views
    0 replies
    Started over 7 years ago
    by Zack Yang
  • Not Answered

    OT but Atmel are no help 0

    2508 views
    0 replies
    Started over 7 years ago
    by Sean Dunlevy
  • Answered

    Understanding XDMAC on Cortex-M7 +1

    • Cortex-M7
    • Cortex-M
    5143 views
    1 reply
    Latest over 7 years ago
    by Vanhealsing
  • Answered

    Looking for an eval board with octa core Armv8 CPU 0

    • AArch64
    18599 views
    11 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    Fixed-point calculation using CMSIS_library 0

    • Cortex-M0
    • Digital Signal Processor (DSP)
    • CMSIS
    • Cortex-M4
    7825 views
    0 replies
    Started over 7 years ago
    by MnP_Junho
  • Not Answered

    MPU and TrustZone 0

    10104 views
    0 replies
    Started over 7 years ago
    by Talk2Joseph
  • Suggested Answer

    Cortex A15 SCU 0

    • Cortex-A15
    • Cortex-A
    12467 views
    1 reply
    Latest over 7 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    WT it non cache able memory when it broadcast at transaction 0

    • Cortex-A53
    • Cortex-A
    11259 views
    1 reply
    Latest over 7 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    reference source code to verify the Cortex-R52 0

    • Cortex-R52
    • Evaluation Boards
    4534 views
    1 reply
    Latest over 7 years ago
    by Jorney
  • Answered

    Where is the register definition of DHCSR for Cortex-M4 +1

    • Cortex-M4
    7590 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    Related from zybo board 0

    9476 views
    0 replies
    Started over 7 years ago
    by Anuj kumar
  • Answered

    aarch64 Exception Level Sw itch from EL1 to EL0 0

    • EL1
    • EL3
    • AArch64
    • Raspberry Pi 3
    • EL0
    • QEMU
    • Cortex-A
    17384 views
    7 replies
    Latest over 7 years ago
    by michaelyuanfeng
  • Not Answered

    when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thanks a lot! 0

    • Cortex-A53
    • Cache
    • Cortex-A
    • Memory
    9980 views
    0 replies
    Started over 7 years ago
    by sam0220
  • Answered

    MMU and Cache configuration 0

    • Cortex-A5
    • Cache
    • Memory Management Unit (MMU)
    • Cortex-A
    24678 views
    12 replies
    Latest over 7 years ago
    by Vanhealsing
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