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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3590 Questions
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  • Not Answered

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    3843 views
    1 reply
    Latest over 4 years ago
    by Andy Neil
  • Answered

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    1 reply
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    by Andy Neil
  • Not Answered

    what is the Instruction L1 TLB and L2 TLB size? 0

    5891 views
    6 replies
    Latest over 4 years ago
    by DANNYWW
  • Not Answered

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    7208 views
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    by DANNYWW
  • Not Answered

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    1519 views
    2 replies
    Latest over 4 years ago
    by Thomas_Stoter
  • Not Answered

    A simple bare-metal GICv3 in AArch64? 0

    • GICv3/v4
    • Generic Interrupt Controller
    • Arm64
    7258 views
    2 replies
    Latest over 4 years ago
    by Andy Neil
  • Not Answered

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    • ROM Memory
    • AArch64
    • Embedded Linux
    • Armv8-A
    • application processor
    • Cortex-A78
    6463 views
    6 replies
    Latest over 4 years ago
    by Neel75
  • Answered

    Are there any ARM processors with hardware H.264 encoder? +1

    • Cortex-M
    36691 views
    10 replies
    Latest over 4 years ago
    by ENRICO
  • Not Answered

    Sampling Interval Problem about SPE (Statistical Profiling Extension) 0

    2761 views
    3 replies
    Latest over 4 years ago
    by YFZ Arm Employee Badge
  • Answered

    【Cortex-M4 with STM32F412RG】 0

    • Cortex-M
    • CMSIS
    • Cortex-M4
    • STM32 F4
    3594 views
    4 replies
    Latest over 4 years ago
    by Kieron Kotaroh Nakamura
  • Suggested Answer

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    3712 views
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    Latest over 4 years ago
    by Andy Neil
  • Answered

    Setting breakpoints at runtime and stepping on the Cortex A53. 0

    6109 views
    9 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    Self hosted debug on Cortex A53, setting up a breakpoint to cause an exception. 0

    2998 views
    1 reply
    Latest over 4 years ago
    by KelvinInIdaho
  • Not Answered

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    • Cortex-A53
    • Cortex-A9
    3160 views
    2 replies
    Latest over 4 years ago
    by BatuhanBulut
  • Answered

    How does cortex-M33, for example, know previous exception priority? 0

    2807 views
    4 replies
    Latest over 4 years ago
    by Susumu Endoh
  • Not Answered

    Where to download IOTKit_CM33_MPS3 FPGA image? 0

    1091 views
    0 replies
    Started over 4 years ago
    by ziming
  • Not Answered

    Error when using Cortex -M3 DesignStart FPGA-Xilinx edition 0

    • FPGA Xilinx
    • Cortex-M3
    • DesignStart
    2133 views
    0 replies
    Started over 4 years ago
    by Shiping
  • Not Answered

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    10998 views
    2 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    What is the execution priority inside WFI for CortexM4? 0

    • Architecture
    • Cortex-M4
    3931 views
    4 replies
    Latest over 4 years ago
    by Jayden Huang
  • Answered

    How should a AXI MASTER or SLAVE behave when a xREADY signal is never asserted? 0

    • AXI
    21503 views
    5 replies
    Latest over 4 years ago
    by Eric KIM
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