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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3584 Questions
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  • Not Answered

    Question about program flow prediction 0

    • Cortex-A
    • Program Flow Trace Macrocell (PTM)
    19474 views
    0 replies
    Started over 6 years ago
    by alireza11048
  • Answered

    How to verify the Cortex-M0 thumb instructions ? I found one chip( RAM &FLASH is OK) when it run LDR relative instructions,the program is in Hardfault。But others run the same code is OK 0

    17431 views
    19 replies
    Latest over 6 years ago
    by hyue
  • Answered

    Cortex-R5 r1p2: Data/Instruction Cache - Configuration during startup, run-time? Specific considerations using RTOS, DMA? +1

    7350 views
    4 replies
    Latest over 6 years ago
    by RLA
  • Not Answered

    About the SBC for standard developing 0

    • Single Board Computer (SBC)
    19299 views
    0 replies
    Started over 6 years ago
    by Miguel87
  • Not Answered

    Function with different types of arguments 0

    2449 views
    1 reply
    Latest over 6 years ago
    by d3x0r
  • Answered

    Arm Cortex-A8 program flow prediction +1

    • Armv7-A
    • Cache
    • Out-of-order Execution
    • Cortex-A
    3951 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Arm Cortex-A8 program flow prediction 0

    • Cache
    • Out-of-order Execution
    • Cortex-A8
    19195 views
    0 replies
    Started over 6 years ago
    by alireza11048
  • Answered

    Shifted binary generated by arm-none-eabi-objcopy +1

    • GCC
    • Cortex-A
    • Cortex-M
    • Baremetal
    10100 views
    8 replies
    Latest over 6 years ago
    by en2senpai
  • Not Answered

    Shifted binary produced by arm-none-eabi-objcopy 0

    • GCC
    20620 views
    0 replies
    Started over 6 years ago
    by en2senpai
  • Not Answered

    Can anybody help me out on reading a Tach signal from DC fan and controlling an LED on/off. MCU - LPC1768 0

    3423 views
    2 replies
    Latest over 6 years ago
    by Trampas
  • Not Answered

    What is arrangement specifier(.16b,.8b) in ARM assembly language instructions? 0

    • SIMD and Vector Processing Instructions
    • Armv8-A
    • NEON
    18966 views
    0 replies
    Started over 6 years ago
    by surajrgupta
  • Not Answered

    Cortex-A15 SOC MPU KEYSTONE 11 AM5K2E04XABDA25-ND AM5K2E04XABD USB3.0 Help to get information and to deal with this processor 0

    18068 views
    0 replies
    Started over 6 years ago
    by Netio
  • Not Answered

    ARMv8 PMU access 0

    • Armv8-A
    19026 views
    0 replies
    Started over 6 years ago
    by Jorge
  • Not Answered

    [CORTEXM4] Tarmac.log in Palladium simulation 0

    4245 views
    2 replies
    Latest over 6 years ago
    by Haiyan Arm Employee Badge
  • Not Answered

    what is the difference between ARM cortex M3 and ARM cortex A9 0

    9441 views
    3 replies
    Latest over 6 years ago
    by Andy Neil
  • Suggested Answer

    CAN program for ARM7 is support for ARM cortex A9 ???? 0

    2756 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Please assist with Usage Fault /Illegal unaligned load or store Cortex M7 Keil MDK-PRO 0

    • Cortex-M7
    • 3 (HardFault)
    • 6 (UsageFault)
    • Debug and Analysis
    8037 views
    4 replies
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    Unable to determine offending instruction: usage fault illegal unaligned load or store cortex m7 keil mdk pro 0

    • Cortex-M7
    • 3 (HardFault)
    • 6 (UsageFault)
    7027 views
    2 replies
    Latest over 6 years ago
    by mzu2006
  • Answered

    When the generic timer starts to tick? 0

    20861 views
    2 replies
    Latest over 6 years ago
    by rzsz
  • Answered

    [DS-5] Is it possible to set a watchpoint on a spec reg? +1

    • DS-5 Debugger
    19577 views
    1 reply
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
<>
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