• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 352 subscribers
  • Views 7210 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

why inner attribute is affected by outer configuration?

geekfolk

Hi expert:

I am configuring a CortexA15 system. In the  LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0  which is used by stage 1 translation.  The problem is, my system behave differently when the outer bits (attr0[7:4]) is set with different value(the value can not be 0). My understanding is,  the system will only be affected by attr0[3:0]. But why attr0[7:4] also make sense now?

Thanks!

Jerry

0