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Hi expert:
I am configuring a CortexA15 system. In the LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0 which is used by stage 1 translation. The problem is, my system behave differently when the outer bits (attr0[7:4]) is set with different value(the value can not be 0). My understanding is, the system will only be affected by attr0[3:0]. But why attr0[7:4] also make sense now?
Thanks!
Jerry
Not necessarily.
The integrated caches in c1,c2,c3 and c4 *might* be configured to be in the same inner shared domain (this would require some hw cache coherency support.) In which case you could make the memory inner shared and inner cacheable.
Or the system could be configured so that the L1&L2 are in different inner shareable domains. Which is like the scenario you describe.