Hi expert:
I am configuring a CortexA15 system. In the LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0 which is used by stage 1 translation. The problem is, my system behave differently when the outer bits (attr0[7:4]) is set with different value(the value can not be 0). My understanding is, the system will only be affected by attr0[3:0]. But why attr0[7:4] also make sense now?
Thanks!
Jerry
Hi Jerry,
The SH bit in the translation table controls shareability. The inner/outer configurations in the MAIR are cacheability.
Different shareability and cacheability settings are independent but will interact with each other in different ways.
Hi Peter,
Thanks for you reply.
What I can't understand is, since mair.attr0[7:4] is for outer cacheability and my system is set as inner shareable, is it still possible that mair.attr0[7:4] can affect the system?
Quite possible,
The outer caches are, roughly speaking, non-integrated caches. These caches might be visible to masters considered as inner shareable.
The system has an arbitrary set of masters that are considered as innershareable. Any inner shareable page must be visible to those masters. If the memory is cacheable this will trigger the hw cache coherency if available. If the caches are not coherent the only way to ensure visibility is for the hw to force that page to be non-cacheable.
I have to go back to the basic concept. Let me use one example to show my doubt:
Core0 & core1 are in one cluster and use integrated L1 and L2 cache to share the data, core2 & core 3 are in another cluster and use their integrated L1 and L2 cache to share the data, moreover non-integrated L3 cache is used to share data in all 4 cores.
So generally speaking, if I only want to share data between core0 & core1, I just need to set core0&core1's SH as innershareable, if I want to share data between all 4 cores, then I have to set their SH as outershareable, is my understanding correct?
Also in the system I describe above, if core2 and core3 are suspended and only core0&core1 are running, I think set SH(for both core0&core1's translation table) as innershareable is ok and mair.attr0[7:4] should not make sense. What is our opinion?
Thanks.
Not necessarily.
The integrated caches in c1,c2,c3 and c4 *might* be configured to be in the same inner shared domain (this would require some hw cache coherency support.) In which case you could make the memory inner shared and inner cacheable.
Or the system could be configured so that the L1&L2 are in different inner shareable domains. Which is like the scenario you describe.