Based on ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags to raise an exception in the processor?
You mean can one set up the environment so floating point zero divide automatically causes an interrupt routine to be called? I'm afraid not. One needs to check the result of a series of operations or use the routines in the fenv.h header to check the exception bits in the floating point status register.
Operations will in general produce NaN (a not-a-number value) if something goes badly wrong. A 1.0/0.0 would produce an Inf (Infinity value). The exception bits in the status are 'sticky', that means they continue being set through further operations unless explicitly reset. These behaviours are so a series of operations can be done with a problem occurring in one of them and the problem can be detected at the end.
Some other systems do support synchronous floating point interrupts but it is becoming uncommon - it requires an appreciable amount of extra hardware design and implementation and the mechanism above works well. If the hardware designers could just continue execution through load and store errors and users had to check a status afterwards they would love it but that would be far harder for programmers to accept ;--)
Not on the A9 as it implements VFPv3 which has a trapless exception model. There is a variant VPF3U that does support generating Arm exceptions based on FP exceptions but this is not available on A9.
FPSCR[15, 12:8] would usually control this behavior but these bits are UNK/SBZP in A9.
Thanks for your reply.
I really need to know which instruction causes the exception in our project. Is there a way to find out these kind of information.