• State Accepted Answer
  • Locked Locked
  • Replies 3 replies
  • Subscribers 352 subscribers
  • Views 5812 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Can Floating Point Unit(FPU) in cortexA9 processor raise an exception?

Yeli

Based on  ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags to raise an exception in the processor?

Parents
  • +1 Arm Employee Badge

    Not on the A9 as it implements VFPv3 which has a trapless exception model.  There is a variant VPF3U that does support generating Arm exceptions based on FP exceptions but this is not available on A9.

    FPSCR[15, 12:8] would usually control this behavior but these bits are UNK/SBZP in A9.

Reply
  • +1 Arm Employee Badge

    Not on the A9 as it implements VFPv3 which has a trapless exception model.  There is a variant VPF3U that does support generating Arm exceptions based on FP exceptions but this is not available on A9.

    FPSCR[15, 12:8] would usually control this behavior but these bits are UNK/SBZP in A9.

Children
No data