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Can Floating Point Unit(FPU) in cortexA9 processor raise an exception?

Yeli over 8 years ago

Based on ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags to raise an exception in the processor?

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daith over 8 years ago +1 verified

You mean can one set up the environment so floating point zero divide automatically causes an interrupt routine to be called? I'm afraid not. One needs to check the result of a series of operations or...
Peter Rielly over 8 years ago +1 verified

Not on the A9 as it implements VFPv3 which has a trapless exception model. There is a variant VPF3U that does support generating Arm exceptions based on FP exceptions but this is not available on A9. ...

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+1 Peter Rielly over 8 years ago

Not on the A9 as it implements VFPv3 which has a trapless exception model. There is a variant VPF3U that does support generating Arm exceptions based on FP exceptions but this is not available on A9.

FPSCR[15, 12:8] would usually control this behavior but these bits are UNK/SBZP in A9.
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+1 Peter Rielly over 8 years ago

Not on the A9 as it implements VFPv3 which has a trapless exception model. There is a variant VPF3U that does support generating Arm exceptions based on FP exceptions but this is not available on A9.

FPSCR[15, 12:8] would usually control this behavior but these bits are UNK/SBZP in A9.
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