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Detect RESET cause on Cortex M3 (STM32F107)?

Terje

Hi.

 

I have a problem HW-resetting an external HW-circuit on my PCB (my MCU is STM32F107):

Because the POWER to my HW-circuits arrives later that to my MCU, I need to (re-) generate a delayed RESET-signal from my MCU towards the RESET-pin of the external HW-circuits.

Q-1: Is there a ”RESET-instruction” (assembly code) that I could use to generate this (common) RESET signal?

Q-2: Is there a way (assembly code) to detect the “reset cause” to avoid repeating (indefinitely) this reset-sequence (the RESET must be done only once)?

Q-3: Or is there an alternative way of achieving this (without modifying the HW by using a GPIO)?

 

Best Regards

Terje Bøhler

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  • +1 Arm Employee Badge in reply to Terje

    Hi there,

    The Cortex-M3 processor itself does not have any instruction to trigger nRST pin directly. Since different chips have different reset circuits, different reset sources (e.g. different types of watchdog, brown out detector), these type of reset control and reset reporting mechanism has to be defined by chip designer (i.e. ST in your case).

    The architectural feature to allow software to generate reset is SYSRESETREQ (System Reset Request). In C programming you can use CMSIS-CORE function NVIC_SystemReset(). This reset the microcontroller system, but does not trigger nRST unless ST add additional feature at chip level to support this.

    regards,

    Joseph

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  • +1 Arm Employee Badge in reply to Terje

    Hi there,

    The Cortex-M3 processor itself does not have any instruction to trigger nRST pin directly. Since different chips have different reset circuits, different reset sources (e.g. different types of watchdog, brown out detector), these type of reset control and reset reporting mechanism has to be defined by chip designer (i.e. ST in your case).

    The architectural feature to allow software to generate reset is SYSRESETREQ (System Reset Request). In C programming you can use CMSIS-CORE function NVIC_SystemReset(). This reset the microcontroller system, but does not trigger nRST unless ST add additional feature at chip level to support this.

    regards,

    Joseph

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