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Which component set the NS bit in SCR ?

Sahil

Hi,

I am new to the ARM TrustZone Architecture.

I am confused that who sets the NS bit in the SCR register, is it the processor itself set bit to 1 when it enters the EL3 mode, or it is the Monitor mode code is setting the NS bit ?

Maybe I am asking some silly question, but I think it is better to ask :-)

Thanks

Sahil

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    Hi Sahil,

    The NS bit is set by the monitor code.

    When you take an exception to EL3 (eg SMC or routed FIQ) the value of SCR_EL3.NS is NOT updated from it's previous value.  This is useful as it allows the monitor code to know the security state the processor was in before entering EL3.

    P

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  • 0

    Hi Sahil,

    The NS bit is set by the monitor code.

    When you take an exception to EL3 (eg SMC or routed FIQ) the value of SCR_EL3.NS is NOT updated from it's previous value.  This is useful as it allows the monitor code to know the security state the processor was in before entering EL3.

    P

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