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Memory map for ARMv8-M TrustZone SOC's

raghu.ncstate

Hello,

I was wondering what the memory map of an SOC that includes a ARMv8-M TrustZone enabled system would like. Is it fixed or is it variable ? Based on the ARMv8-M ARM, it appears that things like the SAU, MPU, NVIC etc are all memory mapped and are expected to be at fixed address. Does this mean there is one SAU and one MPU for an entire SOC even if it includes multiple ARMv8-M cores?

section b7.1 of the ARMv8-M ARM has a system address map which defines addresses and the memory properties. If this address map is fixed, why do we need an MPU which has configurable regions with different memory attributes ?

Thanks

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  • +1 Arm Employee Badge in reply to raghu.ncstate
    Hi Raghu,

    1) Yep :)

    2) Correct. The PPB address range is private to that PE and accesses don't actually go out onto the bus. It effectively reserves some address space to access registers internal to the PE.

    3) It's implementation specific. The SoC would need some extra IP to implement MPU/SAU style protection for non-CPU masters. ARM has some TrustZone controllers in the SIE-200 product but a lot of controllers will use system level MPUs from other vendors.

    4) The NVIC is part of the processor, so extra IP would be needed to dynamically route interrupts to different PEs.

    Pete.
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  • +1 Arm Employee Badge in reply to raghu.ncstate
    Hi Raghu,

    1) Yep :)

    2) Correct. The PPB address range is private to that PE and accesses don't actually go out onto the bus. It effectively reserves some address space to access registers internal to the PE.

    3) It's implementation specific. The SoC would need some extra IP to implement MPU/SAU style protection for non-CPU masters. ARM has some TrustZone controllers in the SIE-200 product but a lot of controllers will use system level MPUs from other vendors.

    4) The NVIC is part of the processor, so extra IP would be needed to dynamically route interrupts to different PEs.

    Pete.
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